# US 10,872,869 B2 · Semiconductor devices and methods of manufacturing the same

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- Number: US 10,872,869 B2
- Document ID: US10872869B2
- Status: Granted
- Kind: B2
- Application number: 16/364,775
- Filed: 2019-03-26
- Published: 2020-02-20
- Granted: 2020-12-22
- Earliest claimed: 2018-08-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jeonggi Jin; Ju-Il Choi; Teahwa Jeong; Atsushi Fujisaki
- Web page: https://patentgrep.com/patent/US10872869B2

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 72/019: {of bond pads}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 72/90: Bond pads, in general
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed are semiconductor devices and methods of manufacturing the same. The method includes providing a semiconductor substrate, forming a redistribution line on a top surface of the semiconductor substrate, and forming a passivation layer to cover the redistribution line on the top surface of the semiconductor substrate. The forming a redistribution line includes a first stage of forming a first segment of the redistribution line on the top surface of the semiconductor substrate, and a second stage of forming a second segment of the redistribution line on the first segment of the redistribution line. An average grain size of the second segment of the redistribution line is less than an average grain size of the first segment of the redistribution line.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate;
forming a redistribution line on a top surface of the semiconductor substrate; and
forming a passivation layer to cover the redistribution line on the top surface of the semiconductor substrate,
wherein the forming the redistribution line includes,
a first stage of forming a first segment of the redistribution line on the top surface of the semiconductor substrate,
a second stage of forming a second segment of the redistribution line on the first segment of the redistribution line, and
a third stage of forming a third segment of the redistribution line on the top surface of the semiconductor substrate before performing the first stage, so that the performing the first stage forms the first segment on the third segment,
wherein an average grain size of the second segment of the redistribution line is less than an average grain size of the first segment of the redistribution line.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first and second stages are successively performed.

### Claim 3 (depends on 2)

The method of claim 2, wherein
each of the first and second stages includes a plating process, and a voltage applied in the first stage is greater than a voltage applied in the second stage.

### Claim 4 (depends on 2)

The method of claim 2, wherein
each of the first and second stages includes a plating process, and
a concentration of a plating solution used for the first stage is greater than a concentration of a plating solution used for the second stage.

### Claim 5 (depends on 2)

The method of claim 2, wherein a plating solution is used for the second stage and includes a grain refiner.

### Claim 6 (depends on 2)

The method of claim 2, wherein the first and second stages are performed in a same bath.

### Claim 7 (depends on 1)

The method of claim 1, wherein a roughness of a bottom surface of the first segment is greater than a roughness of a top surface of the second segment.

### Claim 8 (depends on 1)

The method of claim 1, wherein the average grain size of the second segment of the redistribution line is less than 70% of the average grain size of the first segment of the redistribution line.

### Claim 9 (depends on 1)

The method of claim 1, wherein an average grain size of the third segment of the redistribution line is less than the average grain size of the first segment of the redistribution line.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
etching the passivation layer to expose a portion of the redistribution line; and
forming a pad on the portion of the redistribution line that is exposed by the passivation layer.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
forming a seed layer on the top surface of the semiconductor substrate before forming the redistribution line.

### Claim 12

A semiconductor device, comprising:
a semiconductor substrate;
a redistribution line on a top surface of the semiconductor substrate, the redistribution line including a first segment on the top surface of the semiconductor substrate, a second segment on a top surface of the first segment, and a third segment between the first segment and the semiconductor substrate, an average grain size of the second segment of the redistribution line being less than an average grain size of the first segment of the redistribution line, an average grain size of the third segment is less than the average grain size of the second segment;
a passivation layer covering the redistribution line on the top surface of the semiconductor substrate; and
a pad on the passivation layer, the pad penetrating the passivation layer and in contact with the redistribution line.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a surface roughness of the first segment of the redistribution line is greater than a surface roughness of the second segment of the redistribution line.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the average grain size of the second segment of the redistribution line is less than 70% of the average grain size of the first segment of the redistribution line.

### Claim 15 (depends on 12)

The semiconductor device of claim 12, wherein the second segment of the redistribution line is in contact with the top surface of the first segment and a bottom surface of the passivation layer.

### Claim 16 (depends on 12)

The semiconductor device of claim 12, wherein the first and second segments include a same material.

### Claim 17 (depends on 12)

The semiconductor device of claim 12, further comprising:
a seed layer between the redistribution line and the semiconductor substrate.

### Claim 18 (depends on 12)

The semiconductor device of claim 12, further comprising:
a connection terminal on the pad.