# US 10,872,863 B2 · Semiconductor package

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- Number: US 10,872,863 B2
- Document ID: US10872863B2
- Status: Granted
- Kind: B2
- Application number: 16/216,946
- Filed: 2018-12-11
- Published: 2020-03-05
- Granted: 2020-12-22
- Earliest claimed: 2018-08-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Joo Young Choi; Doo Hwan Lee; Da Hee Kim; Jae Hoon Choi; Byung Ho Kim
- Web page: https://patentgrep.com/patent/US10872863B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/0198: {batch processes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/01261: {Chemical or physical modification, e.g. by sintering or anodisation (patterning H10W72/01251)}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9413: {on encapsulations}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

## Claims

### Claim 1

A semiconductor package comprising:
a connection member having a first surface and a second surface opposing each other and including a plurality of redistribution layers on different levels, the plurality of redistribution layers including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer;
a semiconductor chip disposed on the first surface of the connection member and including a connection pad connected to the at least one second redistribution layer;
an encapsulant disposed on the first surface of the connection member and sealing the semiconductor chip;
a passivation layer disposed on the second surface of the connection member, and including a plurality of openings respectively exposing portions of the first redistribution layer;
a plurality of underbump metallurgy (UBM) layers connected to the portions of the first redistribution layer through the plurality of openings, respectively; and
a plurality of electrical connection structures disposed on the plurality of UBM layers, respectively,
wherein an interface between the passivation layer and the plurality of UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the at least one second redistribution layer, and
wherein the surface roughness of the first unevenness surface and the surface roughness of the second unevenness surface are greater than 1 μm.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the UBM layer comprises a plurality of UBM pads disposed on the passivation layer, and a plurality of UBM vias respectively connecting the plurality of UBM pads to the first redistribution layer through the plurality of openings.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the first unevenness surface is disposed on sidewalls of the plurality of UBM vias respectively located in the plurality of openings.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein the electrical connection structure is disposed to be in contact with the passivation layer around the UBM pad.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the first unevenness surface and the second unevenness surface have different degrees of surface roughness.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the surface roughness of the first unevenness surface and the surface roughness of the second unevenness surface are less than 3 μm.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein the surface roughness of the at least one second redistribution layer is 0.5 μm or less.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the connection member further comprises an insulating member, and the first redistribution layer is disposed on a surface of the insulating member, and the at least one second redistribution layer is disposed in the insulating member.

### Claim 9 (depends on 8)

The semiconductor package of claim 8, wherein the first redistribution layer comprises a redistribution pattern disposed on the surface of the insulating member and a redistribution via disposed in the insulating member to be connected to the redistribution pattern and the at least one second redistribution layer, and
the first unevenness surface is disposed on a surface of the redistribution pattern contacting the passivation layer.

### Claim 10 (depends on 8)

The semiconductor package of claim 8, wherein the at least one second redistribution layer comprises a plurality of second redistribution layers, disposed on different levels in the insulating member, respectively.

### Claim 11 (depends on 8)

The semiconductor package of claim 8, wherein the insulating member comprises a photoimageable insulating material, and the passivation layer comprises a non-photoimageable insulating material.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, further comprising a support member disposed on the first surface of the connection member and having a cavity receiving the semiconductor chip.

### Claim 13

A semiconductor package comprising:
a connection member having a first surface and a second surface opposing each other, and including an insulating member and a plurality of redistribution layers on different levels in the insulating member;
a semiconductor chip disposed on the first surface of the connection member, and including a connection pad connected to the plurality of redistribution layers;
an encapsulant disposed on the first surface of the connection member, and sealing the semiconductor chip;
a passivation layer disposed on the second surface of the connection member;
a plurality of UBM layers including a plurality of UBM pads disposed on the passivation layer, and a plurality of UBM vias passing through the passivation layer, to connect the plurality of UBM pads to the plurality of redistribution layers, respectively; and
a plurality of electrical connection structures respectively disposed on the plurality of UBM pads,
wherein an interface between the passivation layer and the UBM vias has a first unevenness surface, a surface of an outermost redistribution layer among the plurality of redistribution layers has a second unevenness surface, connected to the first unevenness surface, and the outermost redistribution layer has a surface roughness greater than a surface roughness of the other redistribution layers among the plurality of redistribution layers, and
wherein the surface roughness of the first unevenness surface and the surface roughness of the second unevenness surface are greater than 1 μm.

### Claim 14 (depends on 13)

The semiconductor package of claim 13, wherein a surface roughness of the first unevenness surface and a surface roughness of the second unevenness surface are less than 3 μm.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein the first unevenness surface and the second unevenness surface have different degrees of surface roughness.

### Claim 16

A semiconductor package comprising:
a connection member including a first redistribution layer, a second redistribution layer, an insulating layer disposed between the first and second redistribution layers, and a via layer passing the insulating layer and connecting the first and second redistribution layers to each other;
a semiconductor chip disposed on the connection member and including a connection pad connected to the second redistribution layer;
an encapsulant sealing the semiconductor chip;
a passivation layer disposed on the first redistribution layer and including an opening exposing a portion of the first redistribution layer;
an underbump metallurgy (UBM) layer connected to the portion of the first redistribution layer through the opening in the passivation layer; and
an electrical connection structure disposed on the UBM layer,
wherein interfaces between the passivation layer and the UBM layer and between the passivation layer and the first redistribution layer extend continuously from a first contacting portion where the electrical connection structure, the UBM layer, and the passivation layer contact with each other to a second contacting portion where the insulating layer of the connection member, the first redistribution layer, and the passivation layer contact with each other, and have a surface roughness greater than a surface roughness of the second redistribution layer, and
wherein the surface roughness of the interfaces between the passivation layer and the UMB layer and between the passivation layer and the first redistribution layer is greater than 1 μm.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein the interfaces between the passivation layer and the UBM layer and between the passivation layer and the first redistribution layer have different degrees of surface roughness.

### Claim 18 (depends on 16)

The semiconductor package of claim 16, wherein the surface roughness of the interfaces between the passivation layer and the UBM layer and between the passivation layer and the first redistribution layer is less than 3 μm.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, wherein the surface roughness of the second redistribution layer is 0.5 μm or less.

### Claim 20 (depends on 16)

The semiconductor package of claim 16, wherein the insulating layer of the connection member and the passivation layer are made of different materials.