# US 10,872,862 B2 · Package structure having bridge structure for connection between semiconductor dies and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,862 B2 - Document ID: US10872862B2 - Status: Granted - Kind: B2 - Application number: 15/939,288 - Filed: 2018-03-29 - Published: 2019-10-03 - Granted: 2020-12-22 - Earliest claimed: 2018-03-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Chih-Wei Wu; Ying-Ching Shih - Web page: https://patentgrep.com/patent/US10872862B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 72/0198: {batch processes} - H10W 74/10: characterised by their shape or disposition - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 70/63: Vias, e.g. via plugs - H10W 72/072: {of bump connectors} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07236: {Soldering or alloying} - H10W 72/073: {of die-attach connectors} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/354: {comprising polymers} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/728: {between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A package structure including a first semiconductor die, a second semiconductor die, a molding compound, a bridge structure, through insulator vias, an insulating encapsulant, conductive bumps, a redistribution layer and seed layers is provided. The molding compound encapsulates the first and second semiconductor die. The bridge structure is disposed on the molding compound and electrically connects the first semiconductor die with the second semiconductor die. The insulating encapsulant encapsulates the bridge structure and the through insulator vias. The conductive bumps are electrically connecting the first and second semiconductor dies to the bridge structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the bridge structure. The seed layers are respectively disposed in between the through insulator vias and the redistribution layer. ## Claims ### Claim 1 A method of fabricating a package structure, comprising: providing a carrier; forming a redistribution layer on the carrier; disposing a bridge structure and forming a plurality of through insulator vias on the redistribution layer, wherein the plurality of through insulator vias surrounds the bridge structure; forming an insulating material encapsulating the bridge structure and the plurality of through insulator vias; performing a thinning step to form an insulating encapsulant by reducing a thickness of the insulating material until portions of the plurality of through insulator vias and portions of the bridge structure are revealed; forming a dielectric layer on the insulating encapsulant, and patterning the dielectric layer to form a plurality of openings that exposes the portions of the plurality of through insulator vias and conductive posts of the bridge structure for connection; bonding a first semiconductor die and a second semiconductor die to the plurality of through insulator vias and the bridge structure through a plurality of conductive bumps, wherein the bonding of the first semiconductor die and the second semiconductor die are performed after forming the dielectric layer, and the plurality of conductive bumps is physically joined with the plurality of through insulator vias and the bridge structure; forming a molding compound encapsulating the first semiconductor die and the second semiconductor die; de-bonding the carrier; forming a plurality of conductive balls on the redistribution layer; and performing a dicing process cutting through the molding compound, the insulating encapsulant and the redistribution layer, so that sidewalls of the molding compound, the insulating encapsulant and the redistribution layer are levelled. ### Claim 2 (depends on 1) The method according to claim 1, further comprising fitting the plurality of conductive bumps within the plurality of openings to be electrically connected to the bridge structure and the plurality of through insulator vias. ### Claim 3 (depends on 1) The method according to claim 1, wherein the first semiconductor die and the second semiconductor die each comprises a plurality conductive pillars, and the plurality of conductive pillars is electrically connected to the plurality of conductive bumps during bonding. ### Claim 4 (depends on 3) The method according to claim 3, further comprising forming an underfill structure after bonding the first semiconductor die and the second semiconductor die on the insulating encapsulant, wherein the underfill structure fills up the spaces in between each of the conductive pillars. ### Claim 5 (depends on 1) The method according to claim 1, wherein the molding compound is formed to cover backside surfaces of the first semiconductor die and the second semiconductor die. ### Claim 6 (depends on 1) The method according to claim 1, wherein the first semiconductor die has a first sidewall facing the second semiconductor die, the second semiconductor die has a second sidewall facing the first sidewall of the first semiconductor die, and the first semiconductor die and the second semiconductor die are bonded to the bridge structure in a way that the first sidewall and the second sidewall overlap with a silicon bridge of the bridge structure. ### Claim 7 (depends on 1) The method according to claim 1, wherein the bridge structure comprises a silicon bridge, and the plurality of conductive bumps is physically joined with the conductive posts of the bridge structure. ### Claim 8 (depends on 1) The method according to claim 1, further comprising grinding the molding compound to reveal backside surfaces of the first semiconductor die and the second semiconductor die, and forming a heat dissipation layer on the backside surfaces. ### Claim 9 A method of fabricating a package structure, comprising: providing a carrier; forming a redistribution layer on the carrier, the redistribution layer has a first surface and a second surface opposite to the first surface; disposing a bridge structure on the first surface of the redistribution layer; forming a plurality of seed layers on the first surface of the redistribution layer and a plurality of through insulator vias on the plurality of seed layers; forming an insulating encapsulant on the first surface of the redistribution layer encapsulating the bridge structure, the plurality of through insulator vias and the seed layers; forming a dielectric layer on the insulating encapsulant, and patterning the dielectric layer to form a plurality of openings that exposes portions of the plurality of through insulator vias and conductive posts of the bridge structure for connection; bonding a first semiconductor die and a second semiconductor die to the plurality of through insulator vias and the bridge structure through a plurality of conductive bumps, wherein the bonding of the first semiconductor die and the second semiconductor die are performed after forming the dielectric layer, and the first semiconductor die and the second semiconductor die each comprises a plurality of conductive pillars that is physically joined with the plurality of conductive bumps, and the plurality of conductive bumps is physically joined with the plurality of through insulator vias and the bridge structure; forming an underfill structure filling up the spaces in between each of the conductive pillars, wherein the underfill structure covers and is in physical contact with sidewalls of the plurality of conductive pillars; forming a molding compound encapsulating the first semiconductor die and the second semiconductor die; de-bonding the carrier to reveal the second surface of the redistribution layer; and forming a plurality of conductive balls on the second surface of the redistribution layer. ### Claim 10 (depends on 9) The method according to claim 9, wherein the plurality of conductive bumps is located within the plurality of openings to be electrically and physically connected to the bridge structure and the plurality of through insulator vias. ### Claim 11 (depends on 9) The method according to claim 9, wherein each of the first semiconductor die and the second semiconductor die further comprises a semiconductor substrate and a plurality of second seed layers located on the semiconductor substrate, wherein the plurality of second seed layers is sandwiched between the semiconductor substrate and the plurality of conductive pillars. ### Claim 12 (depends on 9) The method according to claim 9, wherein the bridge structure comprises a silicon bridge, and the plurality of conductive bumps is physically joined with the conductive posts of the bridge structure. ### Claim 13 (depends on 9) The method according to claim 9, wherein the molding compound is formed to cover backside surfaces of the first semiconductor die and the second semiconductor die. ### Claim 14 A method of fabricating a package structure, comprising: providing a carrier; forming a redistribution layer on the carrier, wherein the redistribution layer has a first surface and a second surface opposite to the first surface; disposing a bridge structure and forming a plurality of through insulator vias on the first surface of the redistribution layer, wherein the bridge structure comprises a silicon bridge and a plurality of conductive posts, and the plurality of through insulator vias surrounds the bridge structure; forming an insulating encapsulant on the redistribution layer to encapsulate the bridge structure and the plurality of through insulator vias; forming a dielectric layer on the insulating encapsulant, and patterning the dielectric layer to form a plurality of openings that exposes portions of the plurality of through insulator vias and portions of the plurality of conductive posts of the bridge structure for connection; bonding a first semiconductor die and a second semiconductor die to the plurality of through insulator vias and the bridge structure through a plurality of conductive bumps, wherein the first semiconductor die and the second semiconductor die each comprises a plurality of conductive pillars that is physically joined with the plurality of conductive bumps, and the plurality of conductive bumps fills into the plurality of openings of the dielectric layer; forming an underfill structure that simultaneously fills up the spaces in between each of the conductive pillars of the first semiconductor die and the second semiconductor die, and fills up the spaces sandwiched between sidewalls of the first semiconductor die and the second semiconductor die; forming a molding compound encapsulating the first semiconductor die and the second semiconductor die; de-bonding the carrier to reveal the second surface of the redistribution layer; forming a plurality of conductive balls on the second surface of the redistribution layer; and performing a dicing process cutting through the molding compound, the insulating encapsulant and the redistribution layer, so that sidewalls of the molding compound, the insulating encapsulant and the redistribution layer are levelled. ### Claim 15 (depends on 14) The method of fabricating the package structure according to claim 14, wherein the plurality of conductive bumps is physically bonded to the plurality of conductive posts of the bridge structure or physically bonded to the plurality of through insulator vias. ### Claim 16 (depends on 14) The method of fabricating the package structure according to claim 14, further comprises forming a plurality of seed layers on the first surface of the redistribution layer, and forming the plurality of through insulator vias on the plurality of seed layers. ### Claim 17 (depends on 14) The method of fabricating the package structure according to claim 14, wherein the molding compound is formed to cover backside surfaces of the first semiconductor die and the second semiconductor die. ### Claim 18 (depends on 14) The method of fabricating the package structure according to claim 14, wherein the first semiconductor die has the sidewall facing the second semiconductor die, the second semiconductor die has the sidewall facing the sidewall of the first semiconductor die, and the first semiconductor die and the second semiconductor die are bonded to the bridge structure in a way that the sidewalls overlap with the silicon bridge of the bridge structure. ### Claim 19 (depends on 14) The method of fabricating the package structure according to claim 14, wherein the first semiconductor die and the second semiconductor die each comprises a plurality of seed layers and the plurality of conductive pillars located on the plurality of seed layers. ### Claim 20 (depends on 19) The method of fabricating the package structure according to claim 19, wherein the underfill structure further fills up the spaces in between each of the seed layers, and partially covers the sidewalls of the first semiconductor die and the second semiconductor die.