# US 10,872,861 B2 · Semiconductor packages

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,872,861 B2
- Document ID: US10872861B2
- Status: Granted
- Kind: B2
- Application number: 15/891,305
- Filed: 2018-02-07
- Published: 2019-08-08
- Granted: 2020-12-22
- Earliest claimed: 2018-02-07
- Assignees: Advanced Semiconductor Engineering, Inc. Kaohsiung, Taiwan
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Yong-Da Chiu; Shiu-Chih Wang; Shang-Kun Huang; Ying-Ta Chiu; Shin-Luh Tarng; Chih-Pin Hung
- Web page: https://patentgrep.com/patent/US10872861B2

## CPC

- H10W 20/4424: {Copper alloys}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 70/635: {Through-vias}
- H10W 72/90: Bond pads, in general
- H05K 2201/03: Conductive materials
- H05K 2201/09481: Via in pad; Pad over filled via
- H10W 72/01215: {forming coatings}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01255: {by using masks}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/072: {of bump connectors}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/223: {characterised by the structure of the outermost layers, e.g. multilayered coatings}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 76/10: Containers or parts thereof
- H10W 80/314: {characterized by direct bonding of pads or other interconnections}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.

## Claims

### Claim 1

An electrical connection structure, comprising:
a first conductive layer;
a second conductive layer; and
a conductive cup between the first conductive layer and the second conductive layer, the conductive cup having a hardness about one and a half times greater than a hardness of the first conductive layer, and the hardness of the conductive cup ranges from about 1.2 GPa to about 3.1 GPa and is about one and a half times greater than a hardness of the second conductive layer,
wherein the first conductive layer and the conductive cup both include copper.

### Claim 2 (depends on 1)

The electrical connection structure according to claim 1, wherein the conductive cup covers a first surface of the first conductive layer and a second surface of the first conductive layer, and the first surface is oriented at a nonzero angle relative to the second surface.

### Claim 3 (depends on 2)

The electrical connection structure according to claim 2, wherein the conductive cup is a conductive film conformally formed on the first surface and the second surface of the first conductive layer.

### Claim 4 (depends on 3)

The electrical connection structure according to claim 3, wherein a thickness of the conductive film is at least about 0.1 μm.

### Claim 5 (depends on 3)

The electrical connection structure according to claim 3, wherein a thickness of the conductive film is at least about 1 μm.

### Claim 6

A semiconductor package, comprising:
a substrate;
a first conductive layer on the substrate, the first conductive layer including a first plurality of grains;
a second conductive layer on the first conductive layer, the second conductive layer including a second plurality of grains; and
a cup layer between the first conductive layer and the second conductive layer, the cup layer comprising a third plurality of grains,
wherein a number of the third plurality of grains contacting the first conductive layer is greater than a number of the first plurality of grains contacting the cup layer,
the cup layer has a hardness about one and a half times greater than a hardness of the first conductive layer,
the hardness of the cup lay ranges from about 1.2 GPa to about 3.1 GPa and is about one and a half times greater than a hardness of the second conductive layer, and
the first conductive layer and the cup layer both include copper.

### Claim 7 (depends on 6)

The semiconductor package according to claim 6, wherein a number of the third plurality of grains contacting the second conductive layer is greater than a number of the second plurality of grains contacting the cup layer.

### Claim 8 (depends on 6)

The semiconductor package according to claim 6, wherein a third average size of the third plurality of grains is smaller than both a first average size of the first plurality of grains and a second average size of the second plurality of grains.

### Claim 9 (depends on 6)

The semiconductor package according to claim 6, wherein the first conductive layer, the second conductive layer and the cup layer include a same elemental composition.

### Claim 10 (depends on 6)

The semiconductor package according to claim 6, wherein the second conductive layer and the cup layer include a same metal.

### Claim 11 (depends on 6)

The semiconductor package according to claim 6, wherein the second conductive layer includes copper.

### Claim 12 (depends on 6)

The semiconductor package according to claim 6, wherein a first surface of the first conductive layer is oriented at a nonzero angle relative to a second surface of the first conductive layer.

### Claim 13 (depends on 6)

The semiconductor package according to claim 6, wherein a first surface of the first conductive layer is substantially perpendicular to a second surface of the first conductive layer.

### Claim 14

A method of forming an electrical connection structure, comprising:
providing a first conductive layer;
forming a conductive cup on the first conductive layer, a hardness of the conductive cup being about one and a half times greater than a hardness of the first conductive layer, wherein the first conductive layer and the conductive cup both include copper; and
bonding a second conductive layer to the conductive cup, wherein the hardness of the conductive cup ranges from about 1.2 GPa to about 3.1 GPa and is about one and a half times greater than a hardness of the second conductive layer.

### Claim 15 (depends on 14)

The method according to claim 14, wherein forming the conductive cup on the first conductive layer includes plating a copper film on the first conductive layer.

### Claim 16 (depends on 14)

The method according to claim 14, wherein bonding the second conductive layer to the conductive cup is performed under conditions of a temperature in a range from about 200° C. to about 250° C. and a pressure in a range from about 15 MPa to about 20 MPa.