# US 10,872,860 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,860 B2 - Document ID: US10872860B2 - Status: Granted - Kind: B2 - Application number: 16/407,561 - Filed: 2019-05-09 - Published: 2020-05-07 - Granted: 2020-12-22 - Earliest claimed: 2018-11-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Min Sek Jang - Web page: https://patentgrep.com/patent/US10872860B2 ## CPC - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 70/685: comprising multiple insulating layers - H10W 20/42: Vias, e.g. via plugs - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/695: Organic materials - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/90: Bond pads, in general - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 90/00: Package configurations - H10W 90/811: {Multiple chips on leadframes} - H10W 44/20: at high-frequency [HF] or radio frequency [RF] - H10W 46/301: {for alignment} - H10W 46/401: {for identification or tracking} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 70/655: Fan-out layouts - H10W 70/656: Fan-in layouts - H10W 70/68: Shapes or dispositions thereof - H10W 70/682: {comprising holes having chips therein} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer. A frame is disposed on the connection structure and has one or more through-holes. A semiconductor chip and passive components are disposed in the one or more through-holes of the frame on the connection structure. A first encapsulant covers at least portions of the passive components and the frame. A frame wiring layer is disposed on the frame, and a location identifying mark is disposed around the semiconductor chip on the frame and is spaced apart from the frame wiring layer. At least a portion of the location identifying mark is not covered by the first encapsulant. ## Claims ### Claim 1 A semiconductor package comprising: a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer; a frame disposed on the connection structure and having one or more through-holes; a semiconductor chip and passive components disposed in the one or more through-holes of the frame on the connection structure; a first encapsulant covering at least portions of the passive components and the frame and forming a through-hole; a first metal layer disposed on an inner wall of the first encapsulant forming the through-hole; a frame wiring layer disposed on the frame; and a location identifying mark disposed around the semiconductor chip on the frame and spaced apart from the frame wiring layer, wherein at least a portion of the location identifying mark is not covered by the first encapsulant. ### Claim 2 (depends on 1) The semiconductor package of claim 1, further comprising a second encapsulant covering at least a portion of the semiconductor chip. ### Claim 3 (depends on 2) The semiconductor package of claim 2, wherein the second encapsulant covers side surfaces and an upper surface of the semiconductor chip, and the first encapsulant. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor chip and the passive components are disposed in a same through-hole of the one or more through-holes of the frame. ### Claim 5 (depends on 4) The semiconductor package of claim 4, wherein the first encapsulant extends into the same through-hole of the frame, and the semiconductor chip is disposed in the through-hole formed in the first encapsulant that extends into the same through-hole of the frame. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor chip and the passive components are disposed in different through-holes of the one or more through-holes. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein a second metal layer is disposed on inner walls of the frame forming the one or more through-holes. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the location identifying mark takes a form of a metal pattern. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the location identifying mark and the frame wiring layer are formed of the same material as each other. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the location identifying mark is physically and electrically separated from the frame wiring layer. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein the location identifying mark has a symmetrical structure in relation to the through-hole of the frame in which the semiconductor chip is disposed when viewed from above. ### Claim 12 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor chip is disposed so that connection pads of the semiconductor chip face the connection structure. ### Claim 13 A semiconductor package comprising: a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer; a frame disposed on the connection structure and having one or more through-holes; a semiconductor chip and passive components disposed in the one or more through-holes of the frame on the connection structure; a first encapsulant covering at least portions of the passive components and the frame and forming a through-hole; a frame wiring layer disposed on the frame; a location identifying mark disposed around the semiconductor chip on the frame and spaced apart from the frame wiring layer; and a second encapsulant covering at least a portion of the semiconductor chip, wherein at least a portion of the location identifying mark is not covered by the first encapsulant, wherein the second encapsulant covers side surfaces and an upper surface of the semiconductor chip, and the first encapsulant, and wherein the second encapsulant covers an exposed portion of the location identifying mark which is not covered by the first encapsulant. ### Claim 14 A semiconductor package comprising: a frame having an upper surface, a lower surface opposing the upper surface, and a through-hole extending from the upper surface to the lower surface; a semiconductor chip disposed in the through-hole; and a plurality of identifying marks symmetrically disposed relative to the semiconductor chip on the upper surface of the frame, wherein a metal layer is disposed on inner walls of the frame forming the through-hole. ### Claim 15 (depends on 14) The semiconductor package of claim 14, further comprising: a conductive frame wiring layer disposed on the upper surface of the frame, wherein the identifying marks are disposed around the semiconductor chip on the upper surface of the frame to be spaced apart from the conductive frame wiring layer. ### Claim 16 (depends on 15) The semiconductor package of claim 15, wherein the identifying marks and the conductive frame wiring layer are formed of a same material as each other. ### Claim 17 (depends on 14) The semiconductor package of claim 14, further comprising: an encapsulant covering a portion of the frame and extending into the through-hole between the frame and the semiconductor chip, wherein the identifying marks are free of the encapsulant. ### Claim 18 (depends on 17) The semiconductor package of claim 17, further comprising: one or more passive components disposed in the through-hole, electrically connected to the semiconductor chip, and embedded in the encapsulant. ### Claim 19 (depends on 14) The semiconductor package of claim 14, further comprising: a connection structure including a redistribution layer connected to connection pads of the semiconductor chip, wherein the lower surface of the frame is disposed on the connection structure.