# US 10,872,859 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,859 B2 - Document ID: US10872859B2 - Status: Granted - Kind: B2 - Application number: 16/381,243 - Filed: 2019-04-11 - Published: 2020-03-26 - Granted: 2020-12-22 - Earliest claimed: 2018-09-21 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Young Hun Kim; Jae Seok Yang; Hae Wang Lee - Web page: https://patentgrep.com/patent/US10872859B2 ## CPC - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/43: Layouts of interconnections - H10D 30/6219: {characterised by the source or drain electrodes} - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/853: {comprising FinFETs} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/427: {Power or ground buses} - H10W 20/4451: {Semiconductor materials, e.g. polysilicon} - H10W 20/48: Insulating materials thereof - H10W 20/0698: {Local interconnections} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes an active region extending in a first direction on a substrate, a buried conductive layer disposed adjacent to the active region on the substrate and extending in the first direction, a gate electrode intersecting the active region and extending in a second direction crossing the first direction, a source/drain layer disposed on the active region on one side of the gate electrode, a gate isolation pattern disposed on the buried conductive layer so as to be disposed adjacent to one end of the gate electrode, and extending in the first direction, and a contact plug disposed on the source/drain layer, electrically connected to the buried conductive layer, and in contact with the gate isolation pattern. ## Claims ### Claim 1 A semiconductor device comprising: an active region extending in a first direction on a substrate; an isolation layer on a sidewall of the active region; a buried conductive layer extending in the first direction on the substrate such that the buried conductive layer is adjacent to the active region; a gate electrode extending in a second direction crossing the first direction such that the gate electrode intersects the active region; a source/drain layer on the active region on one side of the gate electrode; an interlayer insulating layer on the isolation layer, the buried conductive layer and the source/drain layer; a gate isolation pattern extending in the first direction on the buried conductive layer, the gate isolation pattern penetrating through the interlayer insulating layer; and a contact plug on the source/drain layer, the contact plug including a contact portion extending through the interlayer insulating layer to electrically connect to the buried conductive layer, wherein the gate isolation pattern has a first sidewall and a second sidewall opposing each other, wherein the contact portion of the contact plug is in contact with a first portion of the first sidewall of the gate isolation pattern, wherein one end of the gate electrode faces a second portion of the first sidewall of the gate isolation pattern, and wherein the gate isolation pattern directly contacts at least a portion of the buried conductive layer. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the gate isolation pattern extends continuously along the buried conductive layer. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the gate isolation pattern has a line type in plan view perspective and the gate isolation pattern has a length less than a length of the buried conductive layer in the first direction. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the gate isolation pattern includes portions having different widths in the second direction. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the contact plug is configured to self-align on the buried conductive layer via the sidewall of the gate isolation pattern. ### Claim 6 (depends on 1) The semiconductor device of claim 1, further comprising: an etch stop layer covering a portion of the source/drain layer and a portion of the buried conductive layer, wherein the contact portion covers one end of the source/drain layer and extends to the buried conductive layer and penetrates through the etch stop layer. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the active region includes a recess region, the source/drain layer being on the recess region of the active region, and an upper surface of the buried conductive layer is lower than a bottom of the recess region of the active region with respect to the substrate. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein a lower portion of the buried conductive layer is in the substrate. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the buried conductive layer includes an upper portion and a lower portion, the upper portion being higher than the lower portion with respect to the substrate, and the buried conductive layer has an inclined sidewall such that a width of the upper portion of the buried conductive layer is greater than a width of the lower portion of the buried conductive layer. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the buried conductive layer includes a protruding portion and a lower portion, the lower portion being on the substrate and the protruding portion protruding into the substrate, and a width of the protruding portion is less than a width of the lower portion of the buried conductive layer. ### Claim 11 (depends on 1) The semiconductor device of claim 1, wherein a lower surface of the buried conductive layer is higher than an upper surface of the substrate with respect to the substrate. ### Claim 12 (depends on 1) The semiconductor device of claim 1, further comprising: an insulating layer between the buried conductive layer and the isolation layer and between the buried conductive layer and the substrate. ### Claim 13 A semiconductor device comprising: at least two active regions including a first active region and a second active region, each of the at least two active regions extending in a first direction on a substrate; an isolation layer between the at least two active regions; at least two gate electrodes including a first gate electrode and a second gate electrode, each of the at least two gate electrodes extending in a second direction crossing the first direction such that the at least two gate electrodes are adjacent to each other in the second direction; a buried conductive layer extending in the first direction on the substrate, the buried conductive layer penetrating through at least a portion of the isolation layer; an interlayer insulating layer on the isolation layer, the at least two active regions and the buried conductive layer; a gate isolation pattern on the buried conductive layer, the gate isolation pattern extending in the first direction between the first gate electrode and the second gate electrode and penetrating through the interlayer insulating layer and including a material different from a material of the interlayer insulating layer; at least two source/drain layers including a first source/drain layer and a second source/drain layer on the first active region and the second active region, respectively; and at least two contact plugs including a first contact plug and a second contact plug on the first source/drain layer and the second source/drain layer, respectively, the first contact plug and the second contact plug including a first contact portion and a second contact portion, respectively, the first contact portion and the second contact portion each extending through the interlayer insulating layer to electrically connect to the buried conductive layer such that the first contact portion and the second contact portion that each extend to the buried conductive layer are in contact with a sidewall of the gate isolation pattern while having a laterally asymmetric shape in the second direction, wherein the gate isolation pattern directly contacts at least a portion of the buried conductive layer. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the gate isolation pattern extends in the first direction along the buried conductive layer. ### Claim 15 (depends on 13) The semiconductor device of claim 13, wherein the first contact portion covers one end of the first source/drain layer, and the first contact plug is configured to self-align on the buried conductive layer via the sidewall of the gate isolation pattern. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the second contact portion covers one end of the second source/drain layer, and the second contact plug is configured to self-align on the buried conductive layer via the sidewall of the gate isolation pattern. ### Claim 17 (depends on 13) The semiconductor device of claim 13, wherein a lower portion of the buried conductive layer is in the substrate. ### Claim 18 (depends on 13) The semiconductor device of claim 13, wherein a lower surface of the buried conductive layer is higher than an upper surface of the substrate with respect to the substrate. ### Claim 19 A semiconductor device comprising: a first active fin and a second active fin on a substrate, the first active fin and the second active fin extending in a first direction; a first isolation layer between a first sidewall of the first active fin and a second sidewall of the second active fin, the first sidewall and second sidewall facing each other; a second isolation layer on a third sidewall of the first active fin and on a fourth sidewall of the second active fin, a bottom surface of the second isolation layer at a lower level that a bottom surface of the first isolation layer; a gate electrode extending in a second direction crossing the first direction such that the gate electrode intersects the first active fin and the second active fin; a source/drain layer on the first active fin and the second active fin, a portion of the source/drain layer overlapping the first isolation layer; an interlayer insulating layer on the first isolation layer, the second isolation layer and the source/drain layer; a buried conductive layer extending in the first direction on the substrate, the buried conductive layer having a bottom surface at a lower level than the bottom surface of the second isolation layer; a gate isolation pattern on the buried conductive layer, the gate isolation pattern penetrating through the interlayer insulating layer; and a contact plug on the source/drain layer, the contact plug including a contact portion adjacent to the first active fin and extending along a sidewall of the gate isolation pattern to the buried conductive layer and electrically connecting to the buried conductive layer, wherein the first sidewall and the third sidewall of the first active fin are opposite each other and the second sidewall and the fourth sidewall of the second active fin are opposite each other, and wherein the gate isolation pattern directly contacts at least a portion of the buried conductive layer. ### Claim 20 (depends on 19) The semiconductor device of claim 19, further comprising: an etch stop layer covering a portion of the source/drain layer and a portion of the buried conductive layer; and an insulating layer between the buried conductive layer and the second isolation layer and between the buried conductive layer and the substrate, wherein the contact portion of the contact plug penetrates through the interlayer insulating layer and the etch stop layer.