# US 10,872,858 B2 · Semiconductor memory device

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- Number: US 10,872,858 B2
- Document ID: US10872858B2
- Status: Granted
- Kind: B2
- Application number: 16/027,283
- Filed: 2018-07-04
- Published: 2019-02-28
- Granted: 2020-12-22
- Earliest claimed: 2017-08-30
- Assignees: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicants: United Microelectronics Corp.; Fujian Jinhua Integrated Circuit Co., Ltd.
- Inventors: Hong-Ru Liu; Kuei-Hsuan Yu
- Web page: https://patentgrep.com/patent/US10872858B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10D 89/10: Integrated device layouts
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, and a plurality of bit lines. The semiconductor substrate includes a plurality of active areas. The word lines are disposed parallel to one another, and each of the word lines is elongated in a first direction. Each of the word lines overlaps at least one of the active areas. The bit lines are disposed parallel to one another, and each of the bit lines is elongated in a second direction. Each of the bit lines overlaps at least one of the active areas. The bit lines cross the word lines. An included angle between the first direction and the second direction is larger than 0 degree and smaller than 90 degrees.

## Claims

### Claim 1

A semiconductor memory device, comprising:
a semiconductor substrate comprising active areas;
word lines disposed parallel to one another, and each of the word lines being elongated in a first direction, wherein each of the word lines overlaps at least one of the active areas; and
bit lines disposed parallel to one another, and each of the bit lines being elongated in a second direction, wherein each of the bit lines overlaps at least one of the active areas, the bit lines cross the word lines, and an included angle between the first direction and the second direction is larger than 0 degree and smaller than 90 degrees, wherein each of the active areas is elongated in a third direction, and the third direction is not perpendicular to the first direction and the second direction, wherein an included angle between the third direction and the first direction is smaller than 90 degrees and is larger than the included angle between the first direction and the second direction.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the included angle between the first direction and the second direction is larger than or equal to 45 degrees.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein the included angle between the first direction and the second direction is larger than or equal to 60 degrees.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein the third direction is not parallel to the first direction, and the third direction is not parallel to the second direction.

### Claim 5 (depends on 4)

The semiconductor memory device according to claim 4, wherein an included angle between the third direction and the second direction ranges from 15 degrees to 70 degrees.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein the word lines have a first pitch in the second direction, the bit lines have a second pitch in the first direction, and the second pitch is larger than the first pitch.

### Claim 7 (depends on 6)

The semiconductor memory device according to claim 6, wherein the second pitch is equal to 1.5 times the first pitch.

### Claim 8 (depends on 1)

The semiconductor memory device according to claim 1, wherein each of the active areas is disposed corresponding to two of the word lines.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8, wherein each of the active areas is disposed corresponding to one of the bit lines.