# US 10,872,857 B1 · Three-dimensional memory device containing through-array contact via structures between dielectric barrier walls and methods of making the same

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- Number: US 10,872,857 B1
- Document ID: US10872857B1
- Status: Granted
- Kind: B1
- Application number: 16/444,186
- Filed: 2019-06-18
- Published: 2020-12-24
- Granted: 2020-12-22
- Earliest claimed: 2019-06-18
- Assignees: SanDisk Technologies LLC
- Applicants: Sandisk Technologies LLC
- Inventors: Yoshitaka Otsu; Kei Nozawa; Naoto Hojo; Hirofumi Tokita; Eiji Hayashi; Masanori Terahara
- Web page: https://patentgrep.com/patent/US10872857B1

## CPC

- H10B 43/40: characterised by the peripheral circuit region
- H10W 20/42: Vias, e.g. via plugs
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10B 43/10: characterised by the top-view layout
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/43: Layouts of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

## Claims

### Claim 1

A three-dimensional memory device, comprising:
field effect transistors located over a semiconductor substrate;
lower-level metal interconnect structures formed within lower-level dielectric material layers that overlie the field effect transistors;
an alternating stack of insulating layers and composite layers located over the lower-level metal interconnect structures and between a pair of backside trenches that laterally extend along a first horizontal direction, wherein each of the composite layers comprises a respective electrically conductive layer and a respective dielectric spacer plate, and a vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided within a region including the dielectric spacer plates;
memory stack structures vertically extending through the alternating stack;
a pair of dielectric wall structures vertically extending through each layer within the alternating stack which do not contact each other through another dielectric wall structure, wherein a vertically alternating sequence of the insulating plates and the dielectric spacer plates is located between the pair of dielectric wall structures; and
at least one conductive via structure vertically extending through the vertically alternating sequence and contacting a top surface of a respective one of the lower-level metal interconnect structures.

### Claim 2 (depends on 1)

The three-dimensional memory device of claim 1, wherein the dielectric spacer plates are not completely surrounded by dielectric wall structures.

### Claim 3 (depends on 1)

The three-dimensional memory device of claim 1, wherein each of the dielectric wall structures includes a respective uniform-width region that laterally extend along the first horizontal direction with a respective uniform width along a second horizontal direction that is perpendicular to the first horizontal direction.

### Claim 4 (depends on 3)

The three-dimensional memory device of claim 3, wherein:
each of the dielectric spacer plates comprises lengthwise sidewalls that extend along the first horizontal direction and contacts a respective one of the pair of dielectric wall structures; and
each of the pair of dielectric wall structures has a greater lateral extent than the pair of lengthwise sidewalls of the dielectric spacer plates.

### Claim 5 (depends on 4)

The three-dimensional memory device of claim 4, wherein the pair of dielectric wall structures has a same lateral extent along the first horizontal direction.

### Claim 6 (depends on 4)

The three-dimensional memory device of claim 4, wherein:
the pair of dielectric wall structures are laterally offset along the second horizontal direction from a respective proximal backside trench selected from the pair of backside trenches by unequal lateral trench-to-dielectric spacings; and
a dielectric wall structure of the pair of dielectric wall structures having a greater trench-to-sidewall spacing has a lateral extent along the first horizontal direction that is less than a lateral extent along the first horizontal direction for a dielectric wall structure of the pair of dielectric wall structures having a lesser trench-to-sidewall spacing.

### Claim 7 (depends on 4)

The three-dimensional memory device of claim 4, wherein each of the pair of dielectric wall structures comprises angled sidewalls located within a respective vertical plane that is at an angle in a range from 15 degrees to 75 degrees with respect to a vertical plane including the first horizontal direction.

### Claim 8 (depends on 2)

The three-dimensional memory device of claim 2, wherein each of the pair of dielectric wall structures is located within a respective elongated trench that vertically extends through each layer of the alternating stack and has a greater lateral dimension along the first horizontal direction than along the second horizontal direction.

### Claim 9 (depends on 1)

The three-dimensional memory device of claim 1, wherein each of the dielectric wall structures comprises:
a respective dielectric liner comprising a dielectric material having a different material composition than the dielectric spacer plates; and
a dielectric fill material formed within the respective dielectric liner.

### Claim 10 (depends on 9)

The three-dimensional memory device of claim 9, wherein:
the insulating layers comprise a silicon oxide material;
the dielectric liner comprises a material selected from silicon oxide and a dielectric metal oxide; and
the dielectric spacer plates comprise silicon nitride.

### Claim 11 (depends on 1)

The three-dimensional memory device of claim 1, further comprising drain-select-level isolation structures that vertically extend through a subset of layers within the alternating stack including a topmost one of the composite layers, wherein the drain-select-level isolation structures divide an electrically conductive layer within the topmost one of the composite layers into multiple electrically conductive strips that are electrically isolated from one another.

### Claim 12 (depends on 11)

The three-dimensional memory device of claim 11, wherein each of the multiple electrically conductive strips laterally extends continuously from a first side of the vertically alternating sequence, between a respective one of the pair of backside trenches and a respective one of the dielectric wall structures, and to a second side of the vertically alternating sequence that is laterally spaced from the first side along the first horizontal direction.

### Claim 13 (depends on 11)

The three-dimensional memory device of claim 11, wherein at least one of the drain-select-level isolation structures comprises a first dielectric material segment that has a uniform width and extends along the first horizontal direction, a second dielectric material segment that extends along the first horizontal direction and is laterally offset from the first dielectric material segment by a lateral offset distance, and a connection dielectric material segment connecting the first dielectric material segment and the second dielectric material segment and extending horizontally along a horizontal direction that is at an angle in a range from 15 degrees to 75 degrees with respect to the first horizontal direction.

### Claim 14 (depends on 1)

The three-dimensional memory device of claim 1, further comprising a semiconductor material layer located between the lower-level dielectric material layers and the alternating stack, wherein:
each of the memory stack structures comprises a vertical semiconductor channel and a memory film; and
each sidewall of the pair of dielectric wall structures vertically extend straight from a topmost layer of the alternating stack to a bottommost layer of the alternating stack.

### Claim 15 (depends on 14)

The three-dimensional memory device of claim 14, wherein:
the semiconductor material layer comprises an opening that underlies the vertically alternating sequence; and
the at least one conductive via structure vertically extends through, and contacts, a dielectric material located within the opening in the semiconductor material layer.

### Claim 16

A method for forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a semiconductor substrate, wherein the sacrificial material layers comprise a dielectric material;
forming memory stack structures through the alternating stack;
patterning the alternating stack by performing an anisotropic etch process using a patterned mask layer, wherein the alternating stack is divided into a plurality of alternating stacks of respective insulating layers and respective sacrificial material layers by backside trenches, and wherein a pair of unconnected barrier trenches is formed through each of the plurality of alternating stacks;
forming backside recesses by isotropically etching portions of the sacrificial material layers of the plurality of alternating stacks selective to the insulating layers of the plurality of alternating stacks by introducing an isotropic etchant into the backside trenches while the barrier trenches are covered by a respective dielectric liner that blocks access of the isotropic etchant to adjacent portions of the sacrificial material layers, wherein remaining portions of the sacrificial material layers between each neighboring pair of barrier trenches constitute dielectric spacer plates, and a vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches;
forming electrically conductive layers in the backside recesses; and
forming at least one conductive via structure through the vertically alternating sequence.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
forming field effect transistors on the semiconductor substrate; and
forming lower-level metal interconnect structures formed within lower-level dielectric material layers that overlie the field effect transistors,
wherein:
the vertically-alternating layer stack is formed over the lower-level dielectric material layers; and
the at least one conductive via structure is formed on a respective one of the lower-level metal interconnect structures.

### Claim 18 (depends on 16)

The method of claim 16, further comprising: depositing a dielectric fill material on each of the dielectric liners after formation of the electrically conductive materials, wherein each material portion of the dielectric fill material and a dielectric liner that fills a respective one of the barrier trenches constitutes a dielectric wall structure.

### Claim 19 (depends on 18)

The method of claim 18, wherein each pair of dielectric wall structures formed in a respective pair of barrier trenches has a greater lateral extent than the pair of lengthwise sidewalls of the dielectric spacer plates.

### Claim 20 (depends on 18)

The method of claim 18, wherein each pair of dielectric wall structures formed in a respective pair of barrier trenches comprises angled sidewalls located within a respective vertical plane that is at an angle in a range from 15 degrees to 75 degrees with respect to a vertical plane including the first horizontal direction.