# US 10,872,856 B2 · Semiconductor device including through vias in molded columns

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- Number: US 10,872,856 B2
- Document ID: US10872856B2
- Status: Granted
- Kind: B2
- Application number: 16/277,467
- Filed: 2019-02-15
- Published: 2020-01-02
- Granted: 2020-12-22
- Earliest claimed: 2018-06-28
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Yazhou Zhang; Chin-Tien Chiu; Cong Zhang
- Web page: https://patentgrep.com/patent/US10872856B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 90/00: Package configurations
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is disclosed including a stack of semiconductor die. Openings are formed in the semiconductor die as they are added to the stack, which openings are aligned at different levels of the stack. The openings are filled with an electrically insulative compound to form a molded column through all semiconductor die in the stack. After all semiconductor die are added to the stack, a via may be drilled through the molded column to electrically interconnect each semiconductor die in the stack.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die;
conductive traces on the semiconductor die;
an opening formed through the semiconductor die;
a compound within the opening; and
one or more vias, comprising an electrical conductor, formed within the compound and electrically coupled to one or more conductive trace of the conductive traces;
wherein the conductive traces are formed on a layer attached to the semiconductor die, and wherein the one or more vias are formed through the layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the conductive traces extend into the opening formed through the semiconductor die, the one or more vias formed within the compound lying in physical contact with the conductive traces.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the opening comprises a number of discrete areas, with a via being formed within each discrete area.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the one or more vias comprise a plurality of vias formed in the compound.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the compound is one of a thermoplastic resin and thermosetting polymer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the compound is a cured compound.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the opening comprises a strip across one of the length and width of the semiconductor die.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the opening is along an edge of the semiconductor die.

### Claim 9

A semiconductor device, comprising:
a plurality of stacked semiconductor die;
first means on surfaces of the plurality of stacked semiconductor die for conducting electrical signals;
second means, formed through the plurality of semiconductor dies, for receiving a material;
third means for filling the second means; and
fourth means formed through the third means for conducting electrical signals from the first means;
wherein the first means are formed on a layer attached to the semiconductor die, and wherein the fourth means are formed through the layer.

### Claim 10

A semiconductor device, comprising:
a plurality of stacked semiconductor die;
conductive traces on surfaces of the plurality of stacked semiconductor die;
a plurality of openings, an opening of the plurality of openings formed through each semiconductor die of the plurality of semiconductor dies, wherein the plurality of openings on the plurality of stacked semiconductor dies are aligned with each other;
a compound within the plurality of openings; and
one or more vias, comprising an electrical conductor, formed through the compound in the plurality of openings and electrically coupled to one or more conductive trace of the conductive traces;
wherein the conductive traces extend into the plurality of openings formed through the plurality of semiconductor dies, the one or more vias formed within the compound lying in physical contact with the conductive traces.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the a first semiconductor die of the plurality of semiconductor dies is a controller die, and at least a second semiconductor die of the plurality of semiconductor die is a memory die.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the compound in the plurality of aligned openings comprises a molded column extending through each of the plurality of semiconductor dies.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the plurality of openings comprise a strip across one of the length and width of the plurality of semiconductor dies.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the plurality of openings comprise a number of discrete areas, with a via being formed within each discrete area.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein a via of the one or more vias comprises a hole straight through the plurality of semiconductor dies.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the one or more vias comprise a plurality of vias formed in the compound.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein the compound is one of a thermoplastic resin and thermosetting polymer.

### Claim 18 (depends on 10)

The semiconductor device of claim 10, wherein the conductive traces are formed on a plurality of layers, each attached to a surface of the plurality of semiconductor dies, and wherein the one or more vias are formed through the plurality of layers.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the plurality of openings are not formed through the plurality of layers.