# US 10,872,855 B2 · Chip package and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,855 B2 - Document ID: US10872855B2 - Status: Granted - Kind: B2 - Application number: 16/258,672 - Filed: 2019-01-28 - Published: 2020-01-02 - Granted: 2020-12-22 - Earliest claimed: 2018-06-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Guan-Yu Chen; An-Jhih Su; Der-Chyang Yeh; Li-Hsien Huang; Ming-Shih Yeh - Web page: https://patentgrep.com/patent/US10872855B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 74/01: Manufacture or treatment - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 72/74: {using temporarily an auxiliary support} - H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes} - H10P 72/7404: {the wafer tape being a laminate of three or more layers, e.g. including additional layers beyond a base layer and an uppermost adhesive layer} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 72/0198: {batch processes} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/30: Die-attach connectors - H10W 72/90: Bond pads, in general - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/014: {using batch processing} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10P 72/7438: {with parts of the auxiliary support remaining in the finished device} - H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/655: Fan-out layouts - H10W 72/874: {On different surfaces} - H10W 72/879: {Bump connectors and bond wires} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A chip package including an integrated circuit component, a thermal conductive layer, an insulating encapsulant and a redistribution circuit structure is provided. The integrated circuit component includes an amorphous semiconductor portion located at a back surface thereof. The thermal conductive layer covers the amorphous semiconductor portion of the integrated circuit component, wherein thermal conductivity of the thermal conductive layer is greater than or substantially equal to 10 W/mK. The insulating encapsulant laterally encapsulates the integrated circuit component and the thermal conductive layer. The redistribution circuit structure is disposed on the insulating encapsulant and the integrated circuit component, wherein the redistribution circuit structure is electrically connected to the integrated circuit component. ## Claims ### Claim 1 A method of fabricating a chip package, the method comprising: attaching an integrated circuit component on a carrier through a first thermal paste; forming conductive through vias on the carrier; forming an insulating encapsulant to encapsulate the integrated circuit component and the conductive through vias on the carrier; forming a redistribution circuit structure on the conductive through vias, the insulating encapsulant and the integrated circuit component; after forming the redistribution circuit structure, de-bonding the conductive through vias, the first thermal paste and the insulating encapsulant from the carrier; and electrically connecting a semiconductor device to the conductive through vias such that the first thermal paste is between the integrated circuit component and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit component through the conductive through vias and the redistribution circuit structure. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein thermal conductivity of the first thermal paste ranges from about 10 W/mK to about 250 W/mK. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein a surface of the first thermal paste is revealed after de-bonding the conductive through vias, the first thermal paste and the insulating encapsulant from the carrier, and the revealed surface of the first thermal paste is substantially leveled with a surface of the insualting encapsulation. ### Claim 4 (depends on 1) The method as claimed in claim 1 further comprising: forming an underfill between the integrated circuit component and the semiconductor device to cover the first thermal paste. ### Claim 5 (depends on 1) The method as claimed in claim 1 further comprising: forming a second thermal paste on a surface of the first thermal paste, wherein thermal conductivity of the second thermal paste is greater than or substantially equal to 10 W/mK. ### Claim 6 (depends on 5) The method as claimed in claim 5 further comprising: forming an underfill between the integrated circuit component and the semiconductor device to encapsulate the second thermal paste. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein the integrated circuit component comprises an amorphous semiconductor portion located at a back surface thereof, and the amorphous semiconductor portion of the integrated circuit component is in contact with the first thermal paste. ### Claim 8 A method of fabricating a chip package, the method comprising: providing an integrated circuit component with a metallic layer formed thereon; attaching the integrated circuit component on a carrier through a die attachment film such that the metallic layer is between the integrated circuit component and the die attachment film, wherein thermal conductivity of the metallic layer is greater than thermal conductivity of the die attachment film; forming conductive through vias on the carrier; forming an insulating encapsulant to encapsulate the conductive through vias, the integrated circuit component on the carrier; forming a redistribution circuit structure on the conductive through vias, the insulating encapsulant and the integrated circuit component; after forming a redistribution circuit structure, de-bonding the conductive through vias, the die attachment film and the insulating encapsulant from the carrier; removing the die attachment film to reveal the metallic layer; and electrically connecting a semiconductor device to the conductive through vias such that the die attachment film is between the integrated circuit component and the semiconductor device, wherein the semiconductor device is electrically connected to the integrated circuit component through the conductive through vias and the redistribution circuit structure. ### Claim 9 (depends on 8) The method as claimed in claim 8, wherein thermal conductivity of the die attachment film ranges from about 0.01 W/mK to about 1 W/mK. ### Claim 10 (depends on 8) The method as claimed in claim 8, wherein a surface of the die attachment film is revealed after de-bonding the conductive through vias, the die attachment film and the insulating encapsulant from the carrier. ### Claim 11 (depends on 8) The method as claimed in claim 8 further comprising: forming an underfill between the integrated circuit component and the semiconductor device to cover the metallic layer. ### Claim 12 (depends on 8) The method as claimed in claim 8 further comprising: after removing the die attachment film to revealed the metallic layer, forming a thermal paste on the metallic layer. ### Claim 13 (depends on 12) The method as claimed in claim 12 further comprising: forming an underfill between the integrated circuit component and the semiconductor device to encapsulate the thermal paste. ### Claim 14 (depends on 8) The method as claimed in claim 8, wherein the integrated circuit component comprises an amorphous semiconductor portion located at a back surface thereof, and the amorphous semiconductor portion of the integrated circuit component is in contact with the metallic layer. ### Claim 15 (depends on 8) The method as claimed in claim 8, wherein thermal conductivity of the metallic layer ranges from about 20 W/mK to about 406 W/mK. ### Claim 16 A method, comprising: attaching an integrated circuit component on a carrier through an adhesive; forming conductive through vias on the carrier; forming an insulating encapsulant to encapsulate the adhesive, the integrated circuit component and the conductive through vias on the carrier; forming a redistribution circuit structure on the conductive through vias, the insulating encapsulant and the integrated circuit component; after forming the redistribution circuit structure, de-bonding the adhesive, the conductive through vias and the insulating encapsulant from the carrier; and after de-bonding the adhesive, the conductive through vias and the insulating encapsulant from the carrier, removing the adhesive; and electrically connecting a semiconductor device to the conductive through vias, wherein the semiconductor device is electrically connected to the integrated circuit component through the conductive through vias and the redistribution circuit structure. ### Claim 17 (depends on 16) The method as claimed in claim 16, wherein the integrated circuit component comprises a metallic layer formed on a back surface thereof, and the metallic layer is revealed after removing the adhesive. ### Claim 18 (depends on 17) The method as claimed in claim 17 further comprising: forming a thermal paste on the metallic layer. ### Claim 19 (depends on 16) The method as claimed in claim 16, wherein a recess is formed in the insulating encapsulation after removing the adhesive. ### Claim 20 (depends on 19) The method as claimed in claim 19 further comprising: forming a thermal paste in the recess.