# US 10,872,854 B2 · Electro-optical package and method of fabrication

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- Number: US 10,872,854 B2
- Document ID: US10872854B2
- Status: Granted
- Kind: B2
- Application number: 16/393,763
- Filed: 2019-04-24
- Published: 2019-10-31
- Granted: 2020-12-22
- Earliest claimed: 2018-04-25
- Assignees: Rockley Photonics Limited
- Applicants: Rockley Photonics Limited
- Inventors: Vivek Raghunathan; Vivek Raghuraman; Karlheinz Muth
- Web page: https://patentgrep.com/patent/US10872854B2

## CPC

- G02B 6/4266: {Thermal aspects, temperature control or temperature monitoring (thermal aspect of electrical circuits H05K7/20, H05K5/0213, temperature control in general G05D23/19)}
- G02B 6/4274: {Electrical aspects (G02B6/4263 and G02B6/4265 take precedence)}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/90: Bond pads, in general
- H10F 77/933: {for devices having potential barriers}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/00: Package configurations
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION

## Abstract

An electro-optical package. In some embodiments, the package includes an electronic integrated circuit module, a first electro-optical component, and a photonic integrated circuit. The first electro-optical component may be in a top surface of the photonic integrated circuit. The electronic integrated circuit module may have a top surface facing toward and overlapping both a portion of the first electro-optical component, and a portion of the photonic integrated circuit.

## Claims

### Claim 1

A package, comprising:
an electronic integrated circuit module;
a first electro-optical component; and
a photonic integrated circuit,
the first electro-optical component being in a top surface of the photonic integrated circuit,
the electronic integrated circuit module comprising a redistribution layer and having a top surface facing toward and overlapping:
a portion of the first electro-optical component; and
a portion of the photonic integrated circuit.

### Claim 2 (depends on 1)

The package of claim 1, wherein the electronic integrated circuit module comprises:
an electronic integrated circuit chip having a top surface; and
a plurality of conductors protruding from the top surface of the electronic integrated circuit chip,
wherein the top surface of the electronic integrated circuit chip faces toward and overlaps:
a portion of the first electro-optical component, and
a portion of the photonic integrated circuit; and
wherein a conductive path from the electronic integrated circuit chip to the first electro-optical component extends through a conductor of the plurality of conductors.

### Claim 3 (depends on 1)

The package of claim 1, wherein the electronic integrated circuit module further comprises:
an electronic integrated circuit chip having a top surface, the redistribution layer being on the top surface of the electronic integrated circuit chip; and
a plurality of conductors protruding from a top surface of the redistribution layer,
wherein the top surface of the redistribution layer faces toward and overlaps:
a portion of the first electro-optical component; and
a portion of the photonic integrated circuit, and
wherein a conductive path from the electronic integrated circuit chip to the first electro-optical component extends through a conductor of the plurality of conductors.

### Claim 4 (depends on 3)

The package of claim 3, further comprising an underfill surrounding each of the plurality of conductors.

### Claim 5 (depends on 3)

The package of claim 3, wherein the electronic integrated circuit module comprises a physical medium dependent circuit, configured to interface with the first electro-optical component.

### Claim 6 (depends on 5)

The package of claim 5, wherein the physical medium dependent circuit is in the electronic integrated circuit chip.

### Claim 7 (depends on 5)

The package of claim 5, wherein the physical medium dependent circuit is in a chip, separate from the electronic integrated circuit chip, on a bottom surface of, and connected to, the redistribution layer.

### Claim 8 (depends on 1)

The package of claim 1, wherein the first electro-optical component is a chip embedded in a cavity in the top surface of the photonic integrated circuit.

### Claim 9 (depends on 8)

The package of claim 8, further comprising a eutectic bond between the first electro-optical component and a conductive trace on the top surface of the photonic integrated circuit.

### Claim 10 (depends on 1)

The package of claim 1, wherein the first electro-optical component is integral with the photonic integrated circuit.

### Claim 11 (depends on 1)

The package of claim 1, further comprising a second electro-optical component, wherein:
the first electro-optical component comprises a photodiode chip, and
the second electro-optical component comprises a modulator chip.

### Claim 12

A method for fabricating a package, the method comprising forming a first intermediate product on a first temporary carrier, the forming of the first intermediate product comprising:
forming a redistribution layer on the first temporary carrier;
bonding a via interposer to the redistribution layer;
bonding a photonic integrated circuit to the redistribution layer; and
attaching an electronic integrated circuit module to the via interposer and to the photonic integrated circuit.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
debonding the first intermediate product from the first temporary carrier;
flipping the first intermediate product;
attaching the flipped first intermediate product to a second temporary carrier; and
forming a ball grid array on the redistribution layer.

### Claim 14

A package, comprising:
an electronic integrated circuit module;
a first electro-optical component;
a photonic integrated circuit; and
a via interposer abutting against a top surface of the electronic integrated circuit module,
the first electro-optical component being in a top surface of the photonic integrated circuit,
the top surface of the electronic integrated circuit module facing toward and overlapping:
a portion of the first electro-optical component; and
a portion of the photonic integrated circuit.

### Claim 15 (depends on 14)

The package of claim 14, wherein the via interposer has:
a first surface facing the electronic integrated circuit module;
a second surface opposite the first surface; and
a plurality of conductive vias extending from the first surface to the second surface, and
the conductive vias being respectively electrically connected to a plurality of conductors on the top surface of the electronic integrated circuit module.

### Claim 16 (depends on 15)

The package of claim 15, wherein the via interposer is a separate element from the photonic integrated circuit.

### Claim 17 (depends on 16)

The package of claim 16, wherein the photonic integrated circuit has a cutout to accommodate the via interposer, and the photonic integrated circuit wraps around at least two sides of the via interposer.

### Claim 18 (depends on 17)

The package of claim 17, wherein:
the via interposer is rectangular,
the cutout is a hole, and
the photonic integrated circuit wraps around all four sides of the via interposer.

### Claim 19 (depends on 15)

The package of claim 15, further comprising a redistribution layer having a top surface and a bottom surface, the bottom surface abutting against:
the bottom surface of the photonic integrated circuit; and
the second surface of the via interposer.

### Claim 20 (depends on 19)

The package of claim 19, further comprising a plurality of conductors protruding from the top surface of the redistribution layer.

### Claim 21 (depends on 15)

The package of claim 15, wherein the via interposer is integral with the photonic integrated circuit.

### Claim 22

A hybrid interposer, comprising:
an electro-optical component;
a photonic integrated circuit; and
a via interposer,
the electro-optical component being in a top surface of the photonic integrated circuit,
the via interposer begin adjacent to an edge of the photonic integrated circuit and having:
a first surface substantially level with a top surface of the photonic integrated circuit;
a second surface opposite the first surface; and
a plurality of conductive vias extending from the first surface to the second surface.

### Claim 23 (depends on 22)

The hybrid interposer of claim 22, further comprising a redistribution layer,
the photonic integrated circuit being on a bottom surface of the redistribution layer; and
the via interposer being on the bottom surface of the redistribution layer, a via of the via interposer being connected to a conductor in the redistribution layer.

### Claim 24 (depends on 23)

The hybrid interposer of claim 23, wherein the top surface of the photonic integrated circuit has:
a waveguide mode converter, and
a V-groove,
the V-groove being configured to align an optical fiber to the waveguide mode converter,
the waveguide mode converter being configured to couple light between the optical fiber and the electro-optical component.

### Claim 25 (depends on 24)

The hybrid interposer of claim 24, further comprising a plurality of conductors protruding from a top surface of the redistribution layer.