# US 10,872,852 B2 · Wafer level package utilizing molded interposer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,852 B2 - Document ID: US10872852B2 - Status: Granted - Kind: B2 - Application number: 15/291,086 - Filed: 2016-10-12 - Published: 2018-04-12 - Granted: 2020-12-22 - Earliest claimed: 2016-10-12 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Shing-Yih Shih - Web page: https://patentgrep.com/patent/US10872852B2 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/095: {of vias therein} - H10W 70/685: comprising multiple insulating layers - H10W 70/69: Insulating materials thereof - H10W 74/016: {using moulds} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 90/00: Package configurations - H10P 72/7418: {of passive members, e.g. a chip mounting substrate} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/635: {Through-vias} - H10W 72/0198: {batch processes} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A molded interposer includes a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound for electrically connecting the first RDL structure with the second RDL structure; and a passive device embedded in the layer of first molding compound. ## Claims ### Claim 1 A semiconductor package, comprising: a molded interposer, comprising: a layer of first molding compound having a first side and a second side opposite to the first side; a first redistribution layer (RDL) structure disposed on the first side; a second redistribution layer (RDL) structure disposed on the second side; a plurality of metal vias embedded in the layer of first molding compound electrically connecting the first RDL structure with the second RDL structure; and passive devices, each passive device comprising a first side facing the first RDL structure and an opposite second side facing the second RDL structure, each passive device completely embedded in and completely surrounded by the layer of first molding compound, wherein each passive device is electrically connected to the first RDL structure through a plurality of connecting elements extending directly, vertically between the first RDL structure and the first side of each respective passive device, wherein the plurality of connecting elements are embedded in the layer of first molding compound and surrounded by the layer of first molding compound; semiconductor dice mounted on the first RDL structure and electrically connected thereto on a side of the first RDL structure opposite the passive device, each semiconductor die of the semiconductor dice being electrically connected to, and having a footprint covering, a corresponding one of the passive devices by a direct, vertical connection utilizing the plurality of connecting elements to form a face-to-face connection between each semiconductor die and the corresponding one of the passive devices; and a plurality of solder balls mounted on the second RDL structure. ### Claim 2 (depends on 1) The semiconductor package of claim 1, further comprising: a dummy metal via embedded in the layer of the first molding compound and extending between the first RDL structure and the second RDL structure, the dummy metal via being electrically isolated from signals and positioned for at least one of stress relief or warpage control of the semiconductor package. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the first RDL structure comprises at least one first dielectric layer and at least one first metal layer. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the at least one first dielectric layer comprises an organic material or an inorganic material. ### Claim 5 (depends on 4) The semiconductor package of claim 4, wherein the organic material comprises polyimide. ### Claim 6 (depends on 4) The semiconductor package of claim 4, wherein the inorganic material comprises silicon nitride or silicon oxide. ### Claim 7 (depends on 3) The semiconductor package of claim 3, wherein the at least one first dielectric layer is in direct contact with the layer of first molding compound. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the second RDL structure comprises a second dielectric layer and a second metal layer. ### Claim 9 (depends on 8) The semiconductor package of claim 8, further comprising a solder mask on the second RDL structure. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the layer of first molding compound has a thickness that is thicker than a thickness of the passive device. ### Claim 11 (depends on 1) The semiconductor package of claim 1, wherein the at least one semiconductor die is encapsulated by a layer of second molding compound on the side of the first RDL structure opposite the passive device. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the first molding compound and the layer of second molding compound have different compositions.