# US 10,872,851 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,851 B2 - Document ID: US10872851B2 - Status: Granted - Kind: B2 - Application number: 16/797,513 - Filed: 2020-02-21 - Published: 2020-06-18 - Granted: 2020-12-22 - Earliest claimed: 2018-02-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Eun Jin Kim; Han Kim - Web page: https://patentgrep.com/patent/US10872851B2 ## CPC - H10W 70/685: comprising multiple insulating layers - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 70/65: Shapes or dispositions of interconnections - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 76/13: Containers comprising a conductive base serving as an interconnection - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/9413: {on encapsulations} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a connection member having a first surface and a second surface disposed to oppose each other and including an insulating member having a plurality of insulating layers and a plurality of redistribution layers disposed on the plurality of insulating layers, respectively; a semiconductor chip disposed on the first surface of the connection member and having connection pads electrically connected to the plurality of redistribution layers; and an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, wherein at least one of the plurality of redistribution layers includes a dummy electrode pattern in which a plurality of holes are arranged, and each of the plurality of holes has a shape including a plurality of protruding regions that protrude externally from different positions. ## Claims ### Claim 1 A semiconductor package comprising: a connection member having a first surface and a second surface opposing each other and including an insulating member and a plurality of redistribution layers disposed on different levels of the insulating member; a supporting member disposed on the first surface of the connection member and having a cavity accommodating the semiconductor chip; a semiconductor chip disposed on the first surface of the connection member in the cavity and having connection pads electrically connected to the plurality of redistribution layers; and an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, wherein at least one redistribution layer of the plurality of redistribution layers includes a dummy electrode pattern having a plurality of holes, and each of the plurality of holes has a shape including a plurality of protruding regions that protrude outwardly from different positions on the dummy electrode pattern, wherein a redistribution layer adjacent to the at least one redistribution layer includes a wiring pattern having a region overlapped with the plurality of holes, the wiring pattern of the redistribution layer has a line width narrower than a maximum width of the plurality of holes, and a width of the plurality of protruding regions is less than twice the line width of the wiring pattern of the redistribution layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein a width of the region of the wiring pattern overlapped with the plurality of holes is approximately equal to a width of other regions or is smaller than the width of the other regions by less than 10%. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of holes having a concave polygonal shape. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of holes has the shape selected from a cross shape, a Z shape, an I shape, and a T shape. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein each of the plurality of holes has a cross shape defined as the shape having a central region and four protruding regions protruding from the central region and arranged at an interval of 90°. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the insulating member includes an insulating resin. ### Claim 7 (depends on 1) The semiconductor package of claim 1, further comprising electrical connection structures disposed on the second surface of the connection member, and an underbump metal (UBM) layer electrically connecting the electrical connection structures and the plurality of redistribution layers to each other. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor chip is spaced apart from a side wall of the supporting member by a predetermined distance. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the supporting member includes a wiring structure that connects an upper surface and a lower surface of the supporting member, and the wiring structure is electrically connected to the plurality of redistribution layers. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the different levels of the insulating member include a first level adjacent to the first surface of the connection member and a second level adjacent to the second surface of the connection member, and the plurality of redistribution layers include a first redistribution layer disposed on the first level and connected to the connection pads of the semiconductor chip, and a second redistribution layer disposed on the second level and connected to the first redistribution layer. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein the at least one redistribution layer includes the first redistribution layer. ### Claim 12 (depends on 10) The semiconductor package of claim 10, wherein the plurality of redistribution layers further include a third redistribution layer disposed to be closer to the second surface of the connection member than the second redistribution layer, wherein the at least one redistribution layer further includes the second redistribution layer. ### Claim 13 A semiconductor package comprising: a connection member including an insulating member and a plurality of redistribution layers disposed on different levels of the insulating member; a semiconductor chip disposed on the connection member and having connection pads electrically connected to the plurality of redistribution layers; an encapsulant disposed on a first surface of the connection member and encapsulating the semiconductor chip; and a wiring structure having a bottom end connected to the plurality of redistribution layers and a top end exposing from an upper surface of the encapsulant, wherein at least one redistribution layer of the plurality of redistribution layers includes a dummy electrode pattern having a plurality of holes, and each of the plurality of holes has a concave polygonal shape, wherein a redistribution layer adjacent to the at least one redistribution layer includes a wiring pattern having a region overlapped with the plurality of holes, and the wiring pattern of the redistribution layer has a line width narrower than a maximum width of the plurality of holes, wherein a width of the region of the wiring pattern overlapped with the plurality of holes is approximately equal to a width of other regions or is smaller than the width of the other regions by less than 10%. ### Claim 14 (depends on 13) The semiconductor package substrate of claim 13, wherein each of the plurality of holes has a cross shape having a central region and four protruding regions protruding from the central region. ### Claim 15 (depends on 14) The semiconductor package substrate of claim 14, wherein a width of each of the four protruding regions is less than twice the line width of the wiring pattern of the redistribution layer. ### Claim 16 (depends on 13) The semiconductor package of claim 13, wherein each of the plurality of holes has a shape selected from a cross shape, a Z shape, an I shape, and a T shape. ### Claim 17 A semiconductor package comprising: a connection member having a first surface and a second surface opposing each other and including an insulating member and a plurality of redistribution layers disposed on different levels of the insulating member; a supporting member disposed on the first surface of the connection member and having a cavity accommodating the semiconductor chip; a semiconductor chip disposed on the connection member in the cavity and having connection pads electrically connected to the plurality of redistribution layers; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer disposed on the second surface of the connection member; a plurality of UBM layer disposed on the passivation layer, and electrically connected to the plurality of redistribution layers through an insulating layer; and a plurality of electrical connection structures disposed on the plurality of UBM layers, respectively, wherein the plurality of redistribution layers include a first redistribution layer disposed on a first level and connected to the connection pads of the semiconductor chip, and a second redistribution layer disposed on a second level adjacent to the first level and connected to the first redistribution layer, wherein the first redistribution layer includes a first dummy electrode pattern having a plurality of first holes, each of the plurality of first holes having a concave polygonal shape, and the second redistribution layer includes a wiring pattern having a region overlapped with the plurality of first holes and having a line width narrower than a maximum width of the plurality of first holes, wherein the concave polygonal shape has a central region and a plurality of protruding regions protruding from the central region, a width of each the plurality of protruding regions being less than twice the line width of the wiring pattern of the second redistribution layer. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein a width of the region of the wiring pattern overlapped with the plurality of first holes is approximately equal to a width of other regions or is smaller than the width of the other regions by less than 10%. ### Claim 19 (depends on 17) The semiconductor package of claim 17, wherein the plurality of redistribution layers further include a third redistribution layer disposed to be closer to the second surface of the connection member than the second redistribution layer. ### Claim 20 (depends on 19) The semiconductor package of claim 19, wherein the second redistribution layer further includes a second dummy electrode pattern having a plurality of second holes, each of the plurality of second holes having a concave polygonal shape, and the third redistribution layer includes a wiring pattern having a region overlapped with the plurality of second holes and having a line width narrower than a maximum width of the plurality of second holes.