# US 10,872,845 B2 · Process for manufacturing a flip chip semiconductor package and a corresponding flip chip package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,845 B2 - Document ID: US10872845B2 - Status: Granted - Kind: B2 - Application number: 16/007,767 - Filed: 2018-06-13 - Published: 2018-12-27 - Granted: 2020-12-22 - Earliest claimed: 2017-06-27 - Assignees: STMicroelectronics S.r.l. - Applicants: Stmicroelectronics S.R.L. - Inventors: Mauro Mazzola; Matteo De Santa; Battista Vitali - Web page: https://patentgrep.com/patent/US10872845B2 ## CPC - H10W 70/415: {Leadframe inner leads serving as die pads} - H10W 40/778: {in encapsulations} - H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps} - H10W 70/042: {Etching} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/457: {of metallic layers on leadframes} - H10W 74/016: {using moulds} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/129: {forming a chip-scale package [CSP]} - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07236: {Soldering or alloying} - H10W 72/07237: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07254: {changes in dispositions} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 74/014: {using batch processing} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A process for manufacturing a semiconductor flip chip package and a corresponding flip chip package. The process comprises associating conducting bump pads to a face corresponding to an active side of one or more electronic dice, flipping the one or more electronic dice so that said face corresponding to an active side of one or more electronic dies is facing a leadframe carrying contacting pads in correspondence of said conducting bump pads, bonding said contacting pads to said conducting bump pads and encasing said one or more electronic dice in a casing by a molding operation. The process includes providing a leadframe having contacting pads presenting a recessed surface in correspondence of the position of said conducting bump pads. ## Claims ### Claim 1 An integrated circuit flip chip package, comprising: a semiconductor die including a surface formed by an insulative layer and bond pads; a plurality of leads having first surfaces facing the bond pads, respectively, the first surfaces of the plurality of leads having recesses, respectively; and conductive bumps located in the recesses of the plurality of pads and coupling the bond pads to the plurality of leads, respectively, wherein the first surfaces of the plurality of leads abut the insulative layer at the surface of the semiconductor die. ### Claim 2 (depends on 1) The integrated circuit flip chip package according to claim 1, further comprising conductive filler material in the recesses that aid in coupling the conductive bumps to the plurality of leads. ### Claim 3 (depends on 1) The integrated circuit flip chip package according to claim 1 wherein the recesses of the plurality of leads include finishing layers, respectively. ### Claim 4 (depends on 3) The integrated circuit flip chip package according to claim 3 wherein the finishing layer is gold, gold alloy, silver, or silver alloy. ### Claim 5 (depends on 1) The integrated circuit flip chip package according to claim 1 wherein the semiconductor die includes an insulation layer, the insulation layer including openings that expose the bond pads, wherein the first surfaces of the leads are larger than the openings in the insulation layer. ### Claim 6 A semiconductor package, comprising: a semiconductor die including an active surface that includes a bond pad and an insulation layer, the insulation layer including an opening that exposes the bond pad; a lead having a surface facing the active surface of the semiconductor die, the lead having a recess at the surface, a finishing layer located in the recess; and a conductive bump located in the recess of the lead and between the bond pad and the finishing layer, wherein the conductive bump electrically couples the bond pad to the lead, wherein the surface of the lead overlaps with the insulation layer beyond the opening at the active surface. ### Claim 7 (depends on 6) The semiconductor package according to claim 6, further comprising a conductive filler material in the recess coupled to the conductive bump. ### Claim 8 (depends on 7) The semiconductor package according to claim 7 wherein the filler material is solder or glue. ### Claim 9 (depends on 6) The semiconductor package according to claim 6, wherein the recess includes a solder material that aids in coupling the conductive bump to the lead. ### Claim 10 (depends on 9) The semiconductor package according to claim 9, wherein the finishing layer is one of gold, gold alloy, silver, or silver alloy. ### Claim 11 (depends on 6) The semiconductor package according to claim 6, wherein the surface of the lead abuts the insulation layer. ### Claim 12 A semiconductor package, comprising: a semiconductor die including an active surface, wherein active surface of the semiconductor die includes a bond pad and passivation material, wherein the passivation material is around a perimeter of the bond pad such that a central portion of the bond is exposed from the passivation material; a lead having a surface that is larger than the central portion of the bond pad, the surface of the lead including a recess at the surface, wherein a finishing layer is located in the recess; and a conductive bump located in the recess of the lead and between the bond pad and the finishing layer, wherein the conductive bump electrically couples the bond pad to the lead, wherein the surface of the lead overlaps and abuts the passivation material at the active surface and outwardly of the conductive bump. ### Claim 13 (depends on 12) The semiconductor package according to claim 12, wherein the recess includes a solder material that aids in coupling the conductive bump to the lead. ### Claim 14 (depends on 12) The semiconductor package according to claim 12, wherein the recess has a width that is less than a width of the central portion of the bond pad.