# US 10,872,844 B2 · Semiconductor device with sealed semiconductor chip

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- Number: US 10,872,844 B2
- Document ID: US10872844B2
- Status: Granted
- Kind: B2
- Application number: 16/438,826
- Filed: 2019-06-12
- Published: 2019-09-26
- Granted: 2020-12-22
- Earliest claimed: 2005-05-11
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Isao Ozawa
- Web page: https://patentgrep.com/patent/US10872844B2

## CPC

- H10W 70/40: Leadframes
- H10W 70/415: {Leadframe inner leads serving as die pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor chip with bonding pads, the bonding pads being arranged along one side of an element forming surface of the semiconductor chip, a lead frame including first and second internal leads arranged such that tips thereof correspond to some of the bonding pads of the semiconductor chip, and first and second bonding wires by which the first internal leads and the some of the bonding pads are bonded to each other. The semiconductor device further includes a hanging pin section provided on the element non-forming surface of the semiconductor chip, and a sealing member with which the semiconductor chip is sealed including the hanging pin section and a bonding section between the first and second internal leads and the first and second bonding wires.

## Claims

### Claim 1

A semiconductor device, comprising:
a resin;
a semiconductor chip sealed by the resin and including a plurality of first pads, second pads, and third pads provided along a first side of an orthogonal first surface of the semiconductor chip;
a plurality of first external leads provided outside the resin on a second side opposite to the first side;
a plurality of second external leads provided outside the resin on the first side;
a pair of third external leads provided outside the resin on the first side and the second side, respectively;
a plurality of first internal leads provided in the resin, coupled to the plurality of first external leads, respectively, configured to pass through a second surface opposite to the orthogonal first surface of the semiconductor chip from the second side, and comprising first tips on the first side;
a plurality of second internal leads provided in the resin, coupled to the plurality of second external leads, respectively, and comprising second tips on the first side;
a third internal lead physically directly coupling one of the pair of third external leads on the first side to the other one of the pair of third external leads on the second side;
a plurality of first bonding wires provided in the resin and electrically coupling the first tips of the plurality of first internal leads to the plurality of first pads;
a plurality of second bonding wires provided in the resin and electrically coupling the second tips of the plurality of second internal leads to the plurality of second pads; and
at least one third bonding wire provided in the resin and electrically coupling the third internal lead to at least one of the plurality of third pads.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
hanging pins not electrically coupled to the semiconductor chip in the resin, four of the hanging pins being provided on a third side, and other four of the hanging pins being provided on a fourth side, the third side and the fourth side being sides of the semiconductor chip which intersect the first side and the second side, respectively.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising:
a plurality of fourth external leads provided on the first side and the second side, respectively; and
a plurality of fourth internal leads provided in the resin and coupled to the plurality of fourth external leads.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein tips of the fourth internal leads overlap the semiconductor chip when viewed from above.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the resin above surfaces of the plurality of first internal leads which face the semiconductor chip is larger than a thickness of the resin above surfaces opposite to the surfaces of the plurality of first internal leads which face the semiconductor chip.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein a number of the plurality of second internal leads provided with the plurality of second bonding wires is nine and, when the plurality of second internal leads are divided into a first group including four of the plurality of second internal leads, a second group including other four of the plurality of second internal leads, and a remaining one of the plurality of second internal leads interposed between the first group and the second group, the second tips of the first group and the second group are provided outside of all of the first tips along the first side.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a number of the plurality of second internal leads provided with the plurality of second bonding wires is nine, and a central one of the plurality of second internal leads is adjacent to the third internal lead.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a number of the plurality of first internal leads provided with the plurality of first bonding wires is eight, and the plurality of first internal leads are divided into a group of three and a group of five with the third internal lead interposed therebetween.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein one of the plurality of first internal leads provided with the plurality of first bonding wires has a same potential as one of the plurality of second internal leads provided with the plurality of second bonding wires.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the same potential is a ground potential (VSS).