# US 10,872,838 B1 · Lid for semiconductor electronic package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,838 B1 - Document ID: US10872838B1 - Status: Granted - Kind: B1 - Application number: 16/836,026 - Filed: 2020-03-31 - Granted: 2020-12-22 - Earliest claimed: 2017-03-24 - Assignees: Juniper Networks, Inc. - Applicants: Juniper Networks, Inc. - Inventors: Alexander I. Yatskov; Gautam Ganguly - Web page: https://patentgrep.com/patent/US10872838B1 ## CPC - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 40/037: {Assembling together parts thereof} - H10W 40/226: {characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461)} - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 70/027: {Mechanical treatments, e.g. deforming, punching or cutting} - H10W 76/12: characterised by their shape - H10W 76/15: Containers comprising an insulating or insulated base - H10W 90/00: Package configurations - H10W 40/251: {Organics} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/354: {comprising polymers} - H10W 76/47: Solid or gel fillings - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Techniques are described to limit heat transfer from a first electronic component to a second electronic such as by having an aperture in a lid over the second electronic component to form a gap in the conductance of heat from the first electronic component to the second electronic component. A semiconductor electronic package includes a substrate, a first electronic component that is of a first type and that is mounted along a surface of the substrate, a second electronic component that is of a second type different than the first type and that is mounted along the surface of the substrate, and a metallic component that is positioned over the first electronic component and that has an aperture through which the second electronic component is exposed. ## Claims ### Claim 1 A semiconductor electronic package, comprising: a substrate; a first electronic component that is of a first type and that is mounted along a surface of the substrate; a plurality of second electronic components that are of a second type different than the first type, wherein the plurality of second electronic components are mounted along the surface of the substrate and are spaced apart along the surface of the substrate from the first electronic component; a metallic component that is positioned over the first electronic component and that has an aperture through which the plurality of second electronic components are exposed; a first heat sink coupled to the metallic component to dissipate heat generated by the first electronic component away from the first electronic component; and a second heat sink, mechanically and thermally separate from both the first heat sink and the metallic component, coupled to the plurality of second electronic components to dissipate heat generated by the plurality of second electronic components away from the plurality of second electronic components. ### Claim 2 (depends on 1) The semiconductor electronic package of claim 1, wherein the substrate comprises a silicon interposer. ### Claim 3 (depends on 1) The semiconductor electronic package of claim 1, wherein the first electronic component comprises at least one integrated circuit die. ### Claim 4 (depends on 1) The semiconductor electronic package of claim 1, wherein each one of the plurality of second electronic components comprises at least one memory element. ### Claim 5 (depends on 1) The semiconductor electronic package of claim 1, wherein the metallic component comprises a lid. ### Claim 6 (depends on 1) The semiconductor electronic package of claim 1, wherein the first electronic component has a thermal operating limit greater than the plurality of second electronic components. ### Claim 7 (depends on 1) The semiconductor electronic package of claim 1, further comprising a thermal interface material positioned between and in contact with the metallic component and the first electronic component. ### Claim 8 (depends on 1) The semiconductor electronic package of claim 1, further comprising a thermal interface material positioned over a surface of each one the plurality of second electronic components. ### Claim 9 (depends on 1) The semiconductor electronic package of claim 1, wherein the metallic component is configured to prevent a bending of the semiconductor electronic package and to serve as a heat spreader for the first electronic component. ### Claim 10 A method, comprising: mounting a metallic component to a semiconductor electronic package, the semiconductor electronic package including a first electronic component and a plurality of second electronic components that are of a type different than the first electronic component, wherein the first electronic component is covered by the metallic component, wherein the first electronic component and the plurality of second electronic components are mounted along a surface of a substrate of the semiconductor electronic package, wherein the first electronic component is spaced apart along the surface of the substrate from the plurality of second electronic components, and wherein the plurality of second electronic components are exposed through an aperture of the metallic component; coupling a first heat sink to the metallic component to dissipate heat generated by the first electronic component away from the first electronic component; and coupling a second heat sink, mechanically and thermally separate from both the first heat sink and the metallic component, to the plurality of second electronic components to dissipate heat generated by the plurality of second electronic components away from the plurality of second electronic components. ### Claim 11 (depends on 10) The method of claim 10, wherein the substrate comprises a silicon interposer. ### Claim 12 (depends on 10) The method of claim 10, wherein the first electronic component comprises at least one integrated circuit die. ### Claim 13 (depends on 10) The method of claim 10, wherein each one of the plurality of second electronic components comprises at least one memory element. ### Claim 14 (depends on 10) The method of claim 10, wherein the metallic component comprises a lid. ### Claim 15 (depends on 10) The method of claim 10, wherein the first electronic component has a thermal operating limit greater than the plurality of second electronic components. ### Claim 16 (depends on 10) The method of claim 10, further comprising depositing a thermal interface material on a surface of the first electronic component such that the thermal interface material is positioned between and in contact with the metallic component and the first electronic component after mounting the metallic component to the semiconductor electronic package. ### Claim 17 (depends on 10) The method of claim 10, further comprising depositing a thermal interface material over a surface of each one of the plurality of second electronic components such that the thermal interface material is positioned between and in contact with the second heat sink and the plurality of second electronic components after coupling the second heat sink to the plurality of second electronic components. ### Claim 18 A semiconductor electronic package, comprising: a first electronic component that is of a first type; a plurality of second electronic components that are of a second type different than the first type, wherein the plurality of second electronic components are mounted along a surface of a substrate and are spaced apart along the surface of the substrate from the first electronic component; a metallic component that is positioned over the first electronic component and that has an aperture through which the plurality of second electronic components are exposed; a first heat sink coupled to the metallic component to dissipate heat generated by the first electronic component away from the first electronic component; and a second heat sink, mechanically and thermally separate from both the first heat sink and the metallic component, coupled to the plurality of second electronic components to dissipate heat generated by the plurality of second electronic components away from the plurality of second electronic components. ### Claim 19 (depends on 18) The semiconductor electronic package of claim 18, wherein the first electronic component comprises at least one integrated circuit die. ### Claim 20 (depends on 18) The semiconductor electronic package of claim 18, wherein each one of the plurality of second electronic components comprises at least one memory element.