# US 10,872,836 B2 · Package structure for heat dissipation

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- Number: US 10,872,836 B2
- Document ID: US10872836B2
- Status: Granted
- Kind: B2
- Application number: 16/230,552
- Filed: 2018-12-21
- Published: 2019-04-18
- Granted: 2020-12-22
- Earliest claimed: 2016-12-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Sung-Feng Yeh; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US10872836B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 72/0198: {batch processes}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/635: {Through-vias}
- H10W 70/655: Fan-out layouts
- H10W 72/07204: {using temporary auxiliary members, e.g. sacrificial coatings}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

## Claims

### Claim 1

A device comprising:
a first die, the first die comprising a first set of vias traversing completely through the first die and a first dielectric material surrounding the first set of vias;
a second die, the second die comprising a second set of vias traversing completely through the second die and a second dielectric material surrounding the second set of vias, the first set of vias being aligned with and bonded to the second set of vias, wherein the first dielectric material is bonded to the second dielectric material, and wherein the first set of vias are directly bonded to the second set of vias without solder;
a first molding compound material disposed on sidewalls of the first die; and
a second molding compound material disposed on sidewalls of the second die.

### Claim 2 (depends on 1)

The device of claim 1, wherein the first die and second die form a first die stack, the device further comprising a first substrate, the first substrate comprising a third set of vias disposed therein, the third set of vias being aligned with and bonded to the first set of vias, wherein the first molding compound material is disposed on a top surface of the first substrate.

### Claim 3 (depends on 2)

The device of claim 2, wherein sidewalls of the first die are aligned with sidewalls of the first substrate.

### Claim 4 (depends on 2)

The device of claim 2, further comprising a first heat dissipation feature, the first heat dissipation feature bonded to a logic area of the first substrate, the first heat dissipation feature having a top surface which is aligned with a top surface of the first die stack.

### Claim 5 (depends on 4)

The device of claim 4, wherein the first heat dissipation feature comprises a first number of layers, wherein the first number is the same as a number of dies in the first die stack, wherein each corresponding die in the first die stack and layer in the first heat dissipation feature has the same thickness.

### Claim 6 (depends on 4)

The device of claim 4, wherein the top surface of the first heat dissipation feature and the top surface of the first die stack have grooves disposed therein.

### Claim 7 (depends on 6)

The device of claim 6, further comprising a thermal interface material disposed between the first die stack and the first heat dissipation feature, the thermal interface material extending over the top surface of the first die stack and over the top surface of the first heat dissipation feature.

### Claim 8 (depends on 7)

The device of claim 7, further comprising:
a second substrate, the first substrate attached to the second substrate by a first set of connectors; and
a heat spreader attached to the thermal interface material and to the second substrate.

### Claim 9 (depends on 4)

The device of claim 4, further comprising a second heat dissipation feature, the second heat dissipation feature bonded to a heat dissipating area of the first substrate, the second heat dissipation feature configured the same as the first heat dissipation feature, the second heat dissipation feature having a top surface which is aligned with a top the top surface of the first die stack.

### Claim 10

A die stack structure, comprising:
a first device, comprising a semiconductor substrate, the semiconductor substrate having a metal feature disposed at a surface thereof, the semiconductor substrate comprising active elements;
a second device comprising a substrate and a plurality of conductive vias traversing through an entire thickness of the substrate, wherein the plurality of conductive vias are disposed in the substrate aligned to an adjacent plurality of conductive vias of the first device at a first surface of the second device, wherein a first conductive via of the plurality of conductive vias is bonded to the metal feature of the first device;
a third device comprising a metal feature disposed at a surface of the third device, wherein the metal feature of the third device is bonded to the first conductive via;
a first molding compound material disposed on sidewalls of the second device; and
a second molding compound material disposed on sidewalls of the third device, an outer sidewall of the second molding compound material aligned to an outer sidewall of the semiconductor substrate of the first device.

### Claim 11 (depends on 10)

The die stack structure of claim 10, wherein one or more of the plurality of conductive vias comprises a contact pad.

### Claim 12 (depends on 10)

The die stack structure of claim 10, wherein a contact pad of the first device is bonded to a first conductive via of the second device without a eutectic material, and wherein a first conductive via of the first device is bonded to a second conductive via of the second device without a eutectic material.

### Claim 13 (depends on 10)

The die stack structure of claim 10, wherein molding compound material is disposed on sidewalls of the first device.

### Claim 14 (depends on 10)

The die stack structure of claim 10, wherein each of the first, second, and third devices further comprises:
an top insulating material at a respective top surface; and
a bottom insulating material at a respective bottom surface, wherein at an interface of the first and second devices, the top insulating material of the first device is bonded to the bottom insulating material of the second device.

### Claim 15

A package structure, comprising:
a substrate comprising a logic area and a memory area, a first surface of the substrate having connectors formed thereon, and a second surface of the substrate being opposite the first surface, the logic area comprising a logic device formed in the substrate;
a memory die stack attached to the second surface of the substrate in the memory area;
a first heat dissipating structure attached to the second surface of the substrate in the logic area; and
a thermal interface material disposed over and laterally surrounding the memory die stack and first heat dissipating structure.

### Claim 16 (depends on 15)

The package structure of claim 15, wherein the substrate further comprises a heat dissipating area, the package structure further comprising:
a second heat dissipating structure attached to the second surface of the substrate in the heat dissipating area.

### Claim 17 (depends on 15)

The package structure of claim 15, wherein the first heat dissipating structure comprises a plurality of thermal chips, each of the thermal chips comprising:
a plurality of conductive vias formed in a surrounding material, wherein each of the plurality of conductive vias traverses an entire thickness of the surrounding material.

### Claim 18 (depends on 17)

The package structure of claim 17, wherein a first one of the plurality of thermal chips comprises a plurality of strips of thermal interface material inset into a top surface of the surrounding material.

### Claim 19 (depends on 15)

The package structure of claim 15, wherein the first heat dissipating structure comprises a thermal metal bulk.

### Claim 20 (depends on 15)

The package structure of claim 15, wherein the memory die stack comprises grooves disposed in a top surface of the memory die stack, the thermal interface material filling the grooves.