# US 10,872,835 B1 · Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

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- Number: US 10,872,835 B1
- Document ID: US10872835B1
- Status: Granted
- Kind: B1
- Application number: 16/503,363
- Filed: 2019-07-03
- Published: 2021-01-07
- Granted: 2020-12-22
- Earliest claimed: 2019-07-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Chan H. Yoo; Owen R. Fay
- Web page: https://patentgrep.com/patent/US10872835B1

## CPC

- H10W 40/10: Arrangements for heating
- H05K 7/2039: {characterised by the heat transfer by conduction from the heat generating element to a dissipating body (arrangements for increasing/decreasing heat-transfer, e.g. fins details, F28F13/00)}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H05K 2201/10378: Interposers
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07253: {changes in shapes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/07354: {changes in dispositions}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/354: {comprising polymers}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

## Claims

### Claim 1

A semiconductor assembly, comprising:
a logic device;
a memory device mounted above and overlapping the logic device;
a thermal management layer disposed between the logic device and the memory device, wherein the thermal management layer is configured to reduce vertical transfer of thermal energy between the logic device and the memory device; and
a vertically extending connector electrically coupling the memory device and the logic device, wherein the vertically extending connector extends vertically across the thermal management layer.

### Claim 2 (depends on 1)

The semiconductor assembly of claim 1, wherein the logic device is a graphics processing unit (GPU).

### Claim 3 (depends on 1)

The semiconductor assembly of claim 1, wherein the memory device is a high-bandwidth memory (HBM) device.

### Claim 4 (depends on 1)

The semiconductor assembly of claim 1, wherein the thermal management layer includes a thermally conductive layer configured to transfer the thermal energy across a horizontal plane.

### Claim 5 (depends on 4)

The semiconductor assembly of claim 4, wherein the thermally conductive layer is a graphene structure.

### Claim 6 (depends on 5)

The semiconductor assembly of claim 5, further comprising a heat spreader mounted over the logic device and coupled to peripheral portions of the graphene structure.

### Claim 7 (depends on 6)

The semiconductor assembly of claim 6, wherein the heat spreader includes:
a dissipation portion over the memory device; and
a peripheral portion integral with the dissipation portion and extending vertically toward the logic device, wherein the peripheral portion is directly connected to the peripheral portions of the graphene structure.

### Claim 8 (depends on 1)

The semiconductor assembly of claim 1, wherein the thermal management layer includes a thermal-insulator interposer configured to reduce heat transfer between the logic device and the memory device.

### Claim 9 (depends on 8)

The semiconductor assembly of claim 8, wherein the thermal-insulator interposer includes glass.

### Claim 10 (depends on 8)

The semiconductor assembly of claim 8, wherein the thermal-insulator interposer includes ceramic.

### Claim 11 (depends on 8)

The semiconductor assembly of claim 8, wherein the thermal-insulator interposer includes a cavity.

### Claim 12 (depends on 11)

The semiconductor assembly of claim 11, wherein the cavity is configured to maintain a vacuum condition within the cavity.

### Claim 13 (depends on 11)

The semiconductor assembly of claim 11, wherein the thermal-insulator interposer includes a gas within the cavity.

### Claim 14 (depends on 11)

The semiconductor assembly of claim 11, wherein the thermal-insulator interposer includes a phase change material (PCM) within the cavity.

### Claim 15

A semiconductor assembly, comprising:
a substrate;
a graphics processing unit (GPU) mounted on the substrate;
a memory device mounted above and overlapping the logic device;
a thermal-insulator interposer disposed between the GPU and the memory device and,
wherein the thermal-insulator interposer is configured to reduce vertical transfer of thermal energy between the GPU and the memory device; and
a vertically extending connector electrically coupling the memory device and the GPU,
wherein the vertically extending connector extends vertically across the thermal-insulator interposer.

### Claim 16 (depends on 15)

The semiconductor assembly of claim 15, further comprising:
a graphene layer configured to transfer the thermal energy across a horizontal plane; and
a heat spreader mounted over the GPU and coupled to peripheral portions of the graphene structure, the heat spreader configured to disperse the thermal energy from the GPU.

### Claim 17 (depends on 16)

The semiconductor assembly of claim 16, wherein:
the thermal-insulator interposer includes an opening;
the graphene layer includes a hole; and
the vertically extending connector extends through the opening and the hole.

### Claim 18 (depends on 17)

The semiconductor assembly of claim 17, wherein the opening of the thermal-insulator interposer and the hole of the graphene layer are aligned with a vertical line passing through both the hole and the opening.

### Claim 19 (depends on 18)

The semiconductor assembly of claim 18, further comprising a polymer adhesive in the hole, at least partially encapsulating the graphene layer, and affixing the graphene layer to the GPU.

### Claim 20

A method of manufacturing a semiconductor package, the method comprising:
providing a substrate;
mounting a logic device over the substrate;
providing a graphene layer over the logic device, wherein:
the graphene layer is configured to transfer thermal energy from the logic device across a horizontal plane, and
the graphene layer includes a hole;
attaching a thermal-insulator interposer over the graphene layer, wherein the thermal-insulator interposer includes an opening; and
attaching a memory device over the thermal-insulator interposer and overlapping the logic device, wherein attaching the memory device includes connecting a vertically extending connector between the memory device and the logic device, the vertically extending connector extending vertically through the hole and the opening.