# US 10,872,834 B2 · Integrated circuit structures with extended conductive pathways > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,834 B2 - Document ID: US10872834B2 - Status: Granted - Kind: B2 - Application number: 16/727,584 - Filed: 2019-12-26 - Published: 2020-04-30 - Granted: 2020-12-22 - Earliest claimed: 2019-12-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Yen Hsiang Chew - Web page: https://patentgrep.com/patent/US10872834B2 ## CPC - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 72/00: Interconnections or connectors in packages - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/00: Package configurations - H10W 72/07236: {Soldering or alloying} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/30: Die-attach connectors - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 80/301: {Bonding techniques, e.g. hybrid bonding} - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Integrated circuit (IC) structures with extended conductive pathways, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC structure may include a die having a device side and an opposing back side; a mold compound disposed at the back side; and a conductive pathway extending into the die from the back side and extending into the mold compound from the back side. ## Claims ### Claim 1 An integrated circuit (IC) structure, comprising: a first component, including: a first die having a device side and an opposing back side, a dielectric material at the back side, and a conductive pathway extending into the first die from the back side and extending into the dielectric material from the back side; and a second component conductively coupled to the first component, wherein the second component includes a second die, and the conductive pathway is located in a volume between the second die and the first die. ### Claim 2 (depends on 1) The IC structure of claim 1, wherein the dielectric material has a surface spaced away from the back side such that the back side is between the surface and the device side, and wherein the conductive pathway extends at least to the surface. ### Claim 3 (depends on 2) The IC structure of claim 2, further comprising: an interconnect layer at the surface, wherein the conductive pathway contacts the interconnect layer. ### Claim 4 (depends on 1) The IC structure of claim 1, wherein the second component is conductively coupled to the first component via solder. ### Claim 5 (depends on 1) The IC structure of claim 1, wherein the second component is conductively coupled to the first component by direct bonding. ### Claim 6 (depends on 1) The IC structure of claim 1, wherein the first component includes: a first conductive contact structure in a footprint of the first die, and a second conductive contact structure, coplanar with the first conductive contact structure, outside the footprint of the die. ### Claim 7 (depends on 6) The IC structure of claim 6, wherein the second component is conductively coupled to the first conductive contact structure and the second conductive contact structure. ### Claim 8 (depends on 6) The IC structure of claim 6, wherein the second component is conductively coupled to the first conductive contact structure and a third component, different from the first component and the second component, is conductively coupled to the second conductive contact structure. ### Claim 9 (depends on 3) The IC structure of claim 3, wherein the interconnect layer includes multiple conductive contact structures having a pitch greater than 30 microns. ### Claim 10 (depends on 2) The IC structure of claim 2, wherein a distance between the surface and the back side is greater than a thickness of the die. ### Claim 11 (depends on 1) The IC structure of claim 1, wherein the dielectric material includes a mold compound. ### Claim 12 (depends on 1) The IC structure of claim 1, wherein the conductive pathway includes a first portion in the die and a second portion in the dielectric material, and the second portion is wider than the first portion. ### Claim 13 (depends on 1) The IC structure of claim 1, wherein the die includes a substrate having a front surface and an opposing back surface, the back surface of the substrate provides the back side of the die, and the conductive pathway extends into the die from the back surface to the front surface. ### Claim 14 (depends on 1) The IC structure of claim 1, further comprising: a package substrate; and first-level interconnects coupling the device side of the die to the package substrate. ### Claim 15 (depends on 1) The IC structure of claim 1, wherein the IC structure is part of a wearable computing device. ### Claim 16 (depends on 4) The IC structure of claim 4, wherein the solder is located in the volume between the second component and the die. ### Claim 17 (depends on 5) The IC structure of claim 5, wherein a direct bonding interface between the second component and the first component is located in the volume between the second component and the die. ### Claim 18 (depends on 8) The IC structure of claim 8, wherein the third component includes a die. ### Claim 19 An integrated circuit (IC) structure, comprising: a first component, including: a first die having a device side and an opposing back side, a dielectric material at the back side, and a conductive pathway extending into the die from the back side and extending into the dielectric material from the back side, a first conductive contact structure in a footprint of the first die, wherein the first conductive contact structures includes at least part of the conductive pathway, and a second conductive contact structure, coplanar with the first conductive contact structure, outside the footprint of the die; and a second component conductively coupled to the first component, wherein the second component is conductively coupled to the first conductive contact structure and the second conductive contact structure, the second component includes a second die, and the first conductive contact structure is located in a volume between the first die and the second die. ### Claim 20 An integrated circuit (IC) structure, comprising: a first component, including: a first die having a device side and an opposing back side, a dielectric material at the back side, and a conductive pathway extending into the first die from the back side and extending into the dielectric material from the back side; a second component conductively coupled to the conductive pathway of the first component, wherein the second component includes a second die; a third component, conductively coupled to the second component, wherein the second component is at least partially located in a volume between the second component and the first component; a package substrate; and first-level interconnects coupling the device side of the die to the package substrate.