# US 10,872,829 B2 · Method for repairing a display substrate

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- Number: US 10,872,829 B2
- Document ID: US10872829B2
- Status: Granted
- Kind: B2
- Application number: 16/427,771
- Filed: 2019-05-31
- Published: 2020-04-02
- Granted: 2020-12-22
- Earliest claimed: 2018-09-28
- Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Applicants: Hefei Xinsheng Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd.
- Inventors: Haitao Wang; Guangyao Li; Jun Wang; Qinghe Wang; Ning Liu; Dongfang Wang
- Web page: https://patentgrep.com/patent/US10872829B2

## CPC

- H10P 74/232: {comprising connection or disconnection of parts of a device in response to a measurement}
- G02F 1/136259: {Repairing; Defects}
- G09G 3/006: {Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309)}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/80: characterised by the materials
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/443: {adapted for preventing breakage, peeling or short circuiting}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- G02F 1/136268: {Switch defects}
- G09G 2330/10: Dealing with defective pixels
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A thin film transistor, a display substrate and a method for repairing the same, and a display device are provided. The thin film transistor includes: an active region, a gate insulating layer disposed on a side of the active region, and a gate disposed on a side of the gate insulating layer distal to the active region, and the active region includes a first electrode contact region at one end of the active region, a second electrode contact region at the other end of the active region, and a plurality of connection regions between the first electrode contact region and the second electrode contact region, and each of the plurality of connection regions is coupled to the first electrode contact region and the second electrode contact region, and every two adjacent connection regions are provided with an opening therebetween and are spaced apart from each other by the opening.

## Claims

### Claim 1

A method for repairing a display substrate, wherein
the display substrate comprises a plurality of thin film transistors disposed on a substrate, each of at least part of the plurality of thin film transistors comprises:
an active region,
a gate insulating layer disposed on a side of the active region, and
a gate disposed on a side of the gate insulating layer distal to the active region,
wherein the active region comprises a first electrode contact region at one end of the active region, a second electrode contact region at the other end of the active region opposite to the first electrode contact region, and a plurality of connection regions between the first electrode contact region and the second electrode contact region, and each of the plurality of connection regions is coupled to the first electrode contact region and the second electrode contact region, and every two adjacent connection regions of the plurality of connection regions are provided with an opening therebetween, and are spaced apart from each other by the opening, and
the method comprises:
locating, in the at least part of the plurality of thin film transistors in the display substrate, a thin film transistor of which the gate and at least one of the plurality of connection regions are short-circuited, and
disconnecting the at least one of the plurality connection regions of the thin film transistor from the first contact region and the second contact region of the thin film transistor.

### Claim 2 (depends on 1)

The method of claim 1, wherein the at least part of the plurality of thin film transistors are arranged in an array, the display substrate further comprises a plurality of gate lines extending in a row direction, and among the at least part of the plurality of thin film transistors, gates of the thin film transistors in a same row are coupled to a same gate line.

### Claim 3 (depends on 1)

The method of claim 1, wherein,
the gate insulating layer of each thin film transistor of the at least part of the plurality of thin film transistors is disposed on a side of the active region of the thin film transistor distal to the substrate,
each of the plurality of gate lines covers the plurality of connection regions of each of the thin film transistors in the same row, among the at least part of the plurality of thin film transistors, and
the gate of each thin film transistor of the at least part of the plurality of thin film transistors is formed by a portion of the gate line covering the plurality of connection regions of the thin film transistor.

### Claim 4 (depends on 1)

The method of claim 1, wherein the gate insulating layer of each thin film transistor of the at least part of the plurality of thin film transistors is disposed on a side of the active region of the thin film transistor proximal to the substrate.

### Claim 5 (depends on 1)

The method of claim 1, wherein the number of the plurality of connection regions ranges from 2 to 4.

### Claim 6 (depends on 1)

The method of claim 1, wherein, in a direction perpendicular to a direction that the first electrode contact region is directed to the second electrode contact region, each of the plurality of connection regions has a size ranging from 4 μm to 8 μm, and each opening has a size ranging from 6 μm to 10 μm.

### Claim 7 (depends on 1)

The method of claim 1, wherein the opening is filled with an insulating material.

### Claim 8 (depends on 1)

The method of claim 1, wherein the active region is formed of an oxide semiconductor.

### Claim 9 (depends on 8)

The method of claim 8, wherein the active region is formed of an IGZO material.