# US 10,872,825 B2 · Method of manufacturing a semiconductor device and a semiconductor device

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- Number: US 10,872,825 B2
- Document ID: US10872825B2
- Status: Granted
- Kind: B2
- Application number: 16/281,686
- Filed: 2019-02-21
- Published: 2020-01-02
- Granted: 2020-12-22
- Earliest claimed: 2018-07-02
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hung-Li Chiang; I-Sheng Chen; Tzu-Chiang Chen
- Web page: https://patentgrep.com/patent/US10872825B2

## CPC

- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/364: {of IGFETs}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- H10P 50/642: {Chemical etching}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate. Each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction. A nanowire stack insulating layer is between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures. At least one second stacked nanowire structure is disposed over a second region of the semiconductor substrate, and a shallow trench isolation layer is between the first region and the second region of the semiconductor substrate.

## Claims

### Claim 1

A semiconductor device, comprising:
a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate,
wherein each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction, and the nanowire structures of the first plurality of stacked nanowire structures are arranged along a third direction substantially perpendicular to the first direction and the second direction;
a nanowire stack insulating layer between the substrate and a nanowire closest to the substrate of each nanowire structure of the first plurality of stacked nanowire structures;
at least one second stacked nanowire structure disposed over a second region of the semiconductor substrate; and
a shallow trench isolation layer between the first region and the second region of the semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein there are no shallow trench isolation layers between the stacked nanowire structures of the first plurality of stacked nanowire structures.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first plurality of stacked nanowire structures are disposed over a common mesa structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising a gate structure defining a channel region disposed over each nanowire structure, wherein the gate structure extends in the third direction.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the gate structure wraps around each of the nanowires.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, further comprising source/drains disposed on opposing sides of the gate structure.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the nanowire stack insulating layer includes a first nanowire stack insulating layer made of silicon nitride, silicon carbon nitride, or a low-k material disposed between the source/drain regions and the substrate.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the low-k material is selected from the group consisting of porous silicon dioxide, carbon doped silicon dioxides, and fluorine doped silicon dioxide.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, wherein the nanowire stack insulating layer includes a second nanowire stack insulating in the channel region made of a silicon oxide or a high-k material disposed between the nanowire closest to the substrate and the substrate.

### Claim 10

A semiconductor device, comprising:
a first plurality of stacked nanowire structures extending in a first direction disposed over a first region of a semiconductor substrate,
wherein each nanowire structure of the first plurality of stacked nanowire structures includes a plurality of nanowires arranged in a second direction substantially perpendicular to the first direction, and the nanowire structures of the first plurality of stacked nanowire structures are arranged along a third direction substantially perpendicular to the first direction and the second direction;
at least one second stacked nanowire structure disposed over a second region of the semiconductor substrate,
wherein each nanowire structure of the at least one second stacked nanowire structure includes a plurality of nanowires arranged in the second direction; and
a shallow trench isolation layer between the first region and the second region of the semiconductor substrate,
wherein there is no shallow trench isolation layer between and below a level of the stacked nanowire structures of the first plurality of stacked nanowire structures.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the at least one second stacked nanowire structure disposed over a second region of the semiconductor substrate includes a second plurality of stacked nanowire structures.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein there is no shallow trench isolation layer between and below a level of the stacked nanowire structures of the second plurality of stacked nanowire structures.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the nanowires in each stacked nanowire structure are arranged substantially parallel to each other.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, the first plurality of stacked nanowire structures are disposed over a common mesa structure.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising a gate structure disposed over each nanowire structure, wherein the gate structure extends in the third direction.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate structure wraps around each of the nanowires.

### Claim 17

A semiconductor device, comprising:
a first complementary metal oxide field effect transistor (CMOSFET) disposed over a first mesa structure on a semiconductor substrate,
wherein the first CMOSFET includes a first stacked nanowire structure and a second stacked nanowire structure,
the first and second stacked nanowire structures extend along a first direction, are stacked along a second direction substantially perpendicular to the first direction, and spaced apart from each other along a third direction substantially perpendicular to the first direction and the second direction;
a second CMOSFET disposed over a second mesa structure on the semiconductor substrate,
wherein the second CMOSFET includes a third stacked nanowire structure and a fourth stacked nanowire structure; and
a shallow trench isolation layer disposed between the first mesa structure and the second mesa structure,
wherein there is no shallow trench isolation layer between the first stacked nanowire structure and the second stacked nanowire structure, and
wherein there is no shallow trench isolation layer between the third stacked nanowire structure and the fourth stacked nanowire structure.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a first nanowire stack insulating layer between the first mesa and a nanowire closest to the first mesa of the first stacked nanowire structure; and
a second nanowire stack insulating layer between the second mesa and a nanowire closest to the second mesa of the third stacked nanowire structure.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, further comprising a gate structure disposed over each nanowire structure.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the gate structure wraps around each of the nanowires.