# US 10,872,824 B2 · Si-based high-mobility CMOS device with stacked channel layers and resulting devices

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- Number: US 10,872,824 B2
- Document ID: US10872824B2
- Status: Granted
- Kind: B2
- Application number: 16/280,428
- Filed: 2019-02-20
- Published: 2019-06-13
- Granted: 2020-12-22
- Earliest claimed: 2015-12-22
- Assignees: Imec Vzw
- Applicants: Imec Vzw
- Inventors: Clement Merckling; Guillaume Boccardi
- Web page: https://patentgrep.com/patent/US10872824B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/278: {Pendeoepitaxy}
- H10P 14/3418: {Phosphides}
- H10P 14/3422: {Antimonides}
- H10P 14/3462: {Nanowires}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A device and method for manufacturing a Si-based high-mobility CMOS device is provided. The method includes the steps of: (i) providing a silicon substrate having a first insulation layer on top and a trench into the silicon; (ii) manufacturing a III-V semiconductor channel layer above the first insulation layer by depositing a first dummy layer of a sacrificial material, covering the first dummy layer with a first oxide layer, and replacing the first dummy layer with III-V semiconductor material by etching via holes in the first oxide layer followed by selective area growth; (iii) manufacturing a second insulation layer above the III-V semiconductor channel layer and uncovering the trench; (iv) manufacturing a germanium or silicon-germanium channel layer above the second insulation layer by depositing a second dummy layer of a sacrificial material, covering the second dummy layer with a second oxide layer, and replacing the second dummy layer with germanium or silicon-germanium by etching via holes in the second oxide layer followed by selective area growth.

## Claims

### Claim 1

A Si-based high-mobility CMOS device, the device comprising a silicon substrate having a first insulation layer on top and a plurality of fins extending upwards from the first insulation layer, each fin comprising a stack of layers of uniform thickness, wherein the stack of layers of uniform thickness comprises a germanium or silicon-germanium channel layer for a pMOS device above the first insulation layer, a second insulation layer above the germanium or silicon-germanium channel layer and a III-V semiconductor channel layer for an nMOS device above the second insulation layer, wherein each fin further comprises sources, drains and a common gate of the nMOS device and the pMOS device which are separate for each fin, wherein the nMOS device and the pMOS device are stacked above each other in each fin, wherein portions of the first and second insulation layers are absent such that the III-V semiconductor channel layer and the germanium or silicon-germanium channel layer are nanowires and wherein the common gate is free of the first and second insulation layers, completely surrounds a middle part of the nanowires, and is separated from the sources and drains.

### Claim 2 (depends on 1)

The Si-based high-mobility CMOS device of claim 1, wherein each of the first and second insulation layers is a single layer.

### Claim 3 (depends on 1)

The Si-based high-mobility CMOS device of claim 1, wherein each of the first and second insulation layers are composed of multiple layers.

### Claim 4 (depends on 1)

The Si-based high-mobility CMOS device of claim 1, wherein the III-V semiconductor material is selected from GaP, InxGa(1-x)P, InP, GaAs, InxGa(1-x)As, InAs, GaSb, InxGa(1-x)Sb, or InSb.

### Claim 5 (depends on 1)

The Si-based high-mobility CMOS device of claim 1, wherein each of the first and second insulation layers are composed of oxides.