# US 10,872,821 B1 · Semiconductor structure and manufacturing method thereof

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- Number: US 10,872,821 B1
- Document ID: US10872821B1
- Status: Granted
- Kind: B1
- Application number: 16/450,346
- Filed: 2019-06-24
- Published: 2020-12-24
- Granted: 2020-12-22
- Earliest claimed: 2019-06-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Tung-Jiun Wu
- Web page: https://patentgrep.com/patent/US10872821B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor structure is provided. The method includes: providing a substrate; forming a plurality of fin structures on the substrate; disposing a first dielectric layer over and between the plurality of fin structures; disposing a second dielectric layer over the first dielectric layer; removing a portion of the first dielectric layer and a portion of the second dielectric layer, wherein each of the plurality of fin structures is at least partially exposed through the first dielectric layer and the second dielectric layer; forming a gate structure over the plurality of fin structures; forming an interlayer dielectric (ILD) layer over the first dielectric layer and the second dielectric layer and around the gate structure; removing a portion of the ILD layer; and forming a contact extending into the ILD layer, wherein the contact is disposed above the second dielectric layer. A semiconductor structure thereof is also provided.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a plurality of fin structures on the substrate;
disposing a first dielectric layer over and between the plurality of fin structures;
disposing a second dielectric layer over the first dielectric layer;
removing a portion of the first dielectric layer and a portion of the second dielectric layer, wherein each of the plurality of fin structures is at least partially exposed through the first dielectric layer and the second dielectric layer;
forming a gate structure over the plurality of fin structures;
forming an interlayer dielectric (ILD) layer over the first dielectric layer and the second dielectric layer and around the gate structure;
removing a portion of the ILD layer; and
forming a contact extending into the ILD layer, wherein the contact is disposed above the second dielectric layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the second dielectric layer has an etching rate different from an etching rate of the ILD layer to an etchant.

### Claim 3 (depends on 1)

The method of claim 1, wherein the second dielectric layer includes nitride, and the ILD layer includes oxide.

### Claim 4 (depends on 1)

The method of claim 1, wherein the removing of the portion of the ILD layer comprises:
forming a recess in the ILD layer and stopped at the second dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
disposing a third dielectric layer over the second dielectric layer; and
removing a portion of the third dielectric layer to at least partially expose the plurality of fin structures prior to the formation of the contact.

### Claim 6 (depends on 5)

The method of claim 5, wherein the contact is formed through the ILD layer and into the third dielectric layer.

### Claim 7 (depends on 5)

The method of claim 5, wherein the third dielectric layer and the second dielectric layer have different etching rates to the etchant.

### Claim 8 (depends on 5)

The method of claim 5, wherein the third dielectric layer and the ILD layer include same material.

### Claim 9

A method for manufacturing a semiconductor structure, comprising:
forming a plurality of fin structures and a plurality of micro-fins between the plurality of fin structures on a substrate;
forming a first dielectric layer around the plurality of fin structures and over the plurality of micro-fins;
forming a second dielectric layer over the first dielectric layer and the plurality of micro-fins;
forming an interlayer dielectric (ILD) layer over the first dielectric layer and the second dielectric layer;
performing an etching operation over the ILD layer; and
forming a contact surrounded by the ILD layer and disposed above the second dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein the forming of the plurality of fin structures and the plurality of micro-fins comprises:
forming a plurality of uncut fin structures on the substrate; and
performing a fin cut operation on the plurality of uncut fin structures, thereby forming the plurality of fin structures and a plurality of fin residues between the plurality of fin structures.

### Claim 11 (depends on 10)

The method of claim 10, wherein the forming of the plurality of fin structures and the plurality of micro-fins further comprises:
removing a portion of the substrate between the plurality of fin structures, thereby forming the plurality of micro-fins from the plurality of fin residues and at least one crown structure at a bottom of one or more of the plurality of fin structures.

### Claim 12 (depends on 9)

The method of claim 9, wherein the etching operation comprises:
forming a recess overlapping the plurality of micro-fins from a top view perspective, wherein the recess reaches the second dielectric layer.

### Claim 13 (depends on 9)

The method of claim 9, wherein the forming of the first dielectric layer includes a conformal deposition, and the first dielectric layer fills spaces between the plurality of fin structures.

### Claim 14 (depends on 9)

The method of claim 9, wherein the forming of the second dielectric layer includes a conformal deposition, and a profile of the second dielectric layer is conformal to a profile of the first dielectric layer.

### Claim 15 (depends on 9)

The method of claim 9, wherein the forming of the second dielectric layer includes a blanket deposition, and a top surface of the second dielectric layer is substantially planar and over the plurality of fin structures and the first dielectric layer.

### Claim 16 (depends on 9)

The method of claim 9, wherein the first dielectric layer covers the plurality of micro-fins.

### Claim 17

A method for manufacturing a semiconductor structure, comprising:
forming a plurality of fin structures protruded from a substrate, and a plurality of micro-fins between the plurality of fin structures and protruded from the substrate;
forming an oxide layer surrounding the plurality of fin structures and covering the plurality of micro-fins;
forming a nitride layer surrounded by the oxide layer and disposed above the plurality of micro-fins;
forming an interlayer dielectric (ILD) layer over the oxide layer and the nitride layer and surrounding the plurality of fin structures; and
forming a contact extending through the ILD and disposed above the plurality of micro-fins, the oxide layer and the nitride layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the contact is disposed above the plurality of fin structures.

### Claim 19 (depends on 17)

The method of claim 17, wherein a top surface of the ILD is substantially coplanar with a top surface of the contact.

### Claim 20 (depends on 17)

The method of claim 17, wherein a thickness of the nitride layer is in a range of 20 to 40 nm.