# US 10,872,820 B2 · Integrated circuit structures

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- Number: US 10,872,820 B2
- Document ID: US10872820B2
- Status: Granted
- Kind: B2
- Application number: 16/316,330
- Filed: 2017-08-25
- Published: 2020-01-30
- Granted: 2020-12-22
- Earliest claimed: 2016-08-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Bruce Block; Valluri R. Rao; Patrick Morrow; Rishabh Mehandru; Doug Ingerly; Kimin Jun; Kevin O'Brien; Paul Fischer; Szyua S. Liao
- Web page: https://patentgrep.com/patent/US10872820B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/101: {comprising components on opposite major surfaces of semiconductor substrates}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R 31/2889: {Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/679: {comprising air gaps}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/82: of only field-effect components
- H10D 84/853: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 52/402: {of semiconductor materials}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 95/11: {Separation of active layers from substrates}
- H10W 20/43: Layouts of interconnections
- H10W 20/4424: {Copper alloys}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 72/019: {of bond pads}
- H10W 72/90: Bond pads, in general
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- G01R 1/07307: {with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7426: {used as a support during build up manufacturing of active devices}
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 90/00: Package configurations
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/722: {between stacked chips}
- H10W 90/792: {between multiple chips}
- Y02E 10/50: Photovoltaic [PV] energy
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

## Claims

### Claim 1

A device structure, comprising:
a body, comprising a monocrystalline semiconductor material, adjacent to an isolation dielectric;
a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
a source and a drain coupled to the body on opposite sides of the gate stack;
a front-side interconnect metallization layer coupled to at least one of the source, drain, or gate electrode; and
a back-side device layer over a back-side surface of the body, opposite the front-side interconnect metallization layer, wherein the back-side device layer comprises a second semiconductor material having a different composition than that of the body; and
a back-side device terminal electrically coupled to the back-side device layer, wherein:
the structure comprises a first field effect transistor (FET) stacked over a second FET;
the second semiconductor material is monocrystalline;
a second gate stack is coupled to the second semiconductor material; and
the back-side device terminal further comprises a source or a drain of the second FET, which is coupled to the second semiconductor material.

### Claim 2 (depends on 1)

The structure of claim 1, wherein:
the monocrystalline semiconductor material comprises a first Group IV or Group III-V semiconductor; and
the second semiconductor material comprises a second Group IV or Group III-V semiconductor.

### Claim 3 (depends on 1)

The structure of claim 1, further comprising:
a back-side interconnect metallization layer coupled to the back-side device terminal, wherein
the body and the back-side device layer are located between the front-side interconnect metallization layer and the back-side interconnect metallization layer.

### Claim 4 (depends on 1)

The structure of claim 1, wherein the back-side device terminal is in contact with one of the source or drain of the FET.

### Claim 5 (depends on 1)

The structure of claim 1, wherein
the back-side interconnect metallization layer has a different composition than the front-side interconnect metallization layer.

### Claim 6 (depends on 5)

The structure of claim 5, wherein:
the front-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the back-side interconnect metallization layer, or the back-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the front-side interconnect metallization layer.

### Claim 7 (depends on 6)

The IC structure of claim 6, wherein the front-side interconnect metallization layer comprises one or more of Ru, Rh, Pd, Jr, Pt, Au, W, Cr, or Co, and the back-side interconnect metallization layer comprises Cu.

### Claim 8

A device structure, comprising:
a body, comprising a monocrystalline semiconductor material, adjacent to an isolation dielectric;
a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
a source and a drain coupled to the body on opposite sides of the gate stack;
a front-side interconnect metallization layer coupled to at least one of the source, drain, or gate electrode; and
a back-side device layer over a back-side surface of the body, opposite the front-side interconnect metallization layer, wherein the back-side device layer comprises a second semiconductor material having a different composition than that of the body; and
a back-side device terminal electrically coupled to the back-side device layer, wherein:
the structure comprises a field effect transistor (FET) stacked over a thin film transistor (TFT);
the second semiconductor material is polycrystalline or amorphous;
a second gate stack is coupled to the second semiconductor material; and
the back-side device terminal further comprises a source or drain of the TFT, which is coupled to the second semiconductor material.

### Claim 9

An integrated circuit (IC) structure, comprising:
a transistor body adjacent to a field isolation dielectric, the transistor body comprising a monocrystalline semiconductor material;
a gate stack adjacent to a sidewall of the body, the gate stack including a gate electrode separated from the sidewall by a gate dielectric;
a source and a drain coupled to the transistor body on opposite sides of the gate stack;
a front-side interconnect metallization layer over a first side of the transistor body and the field isolation dielectric, the front-side interconnect metallization layer coupled to a first one of the source, drain, or gate electrode; and
a back-side interconnect metallization layer over a second side of the body and the field isolation dielectric, the back-side interconnect metallization layer coupled to a second one of the source, drain, or gate electrode, and wherein the front-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the back-side interconnect metallization layer, or the back-side interconnect metallization layer comprises an alloy having more Cu than any metal alloy of the front-side interconnect metallization layer.

### Claim 10 (depends on 9)

The IC structure of claim 9, wherein the front-side interconnect metallization layer comprises one or more of Ru, Rh, Pd, Jr, Pt, Au, W, Cr, or Co, and the back-side interconnect metallization layer comprises Cu.

### Claim 11 (depends on 10)

The IC structure of claim 10, wherein the back-side interconnect layer is coupled to the source, the front-side interconnect layer is coupled to the gate electrode, and the back-side interconnect metallization layer comprises features having at least one of larger lateral dimensions or greater thickness than the front-side interconnect metallization layer.