# US 10,872,818 B2 · Buried power rail and method forming same

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- Number: US 10,872,818 B2
- Document ID: US10872818B2
- Status: Granted
- Kind: B2
- Application number: 16/293,858
- Filed: 2019-03-06
- Published: 2020-04-30
- Granted: 2020-12-22
- Earliest claimed: 2018-10-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Chiang; Shi Ning Ju; Kuan-Lun Cheng; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US10872818B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/021: {of interconnections within wafers or substrates}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/076: {in via holes or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/427: {Power or ground buses}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes etching a semiconductor substrate to form two semiconductor strips. The two semiconductor strips are over a bulk portion of the semiconductor substrate. The method further includes etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate, forming a liner dielectric layer lining the trench, forming a buried contact in the trench, forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips, and forming isolation regions on opposite sides of the two semiconductor strips. The buried power rail is underlying a portion of the isolation regions.

## Claims

### Claim 1

A method of forming an integrated circuit structure, the method comprising:
etching a semiconductor substrate to form two semiconductor strips, wherein the two semiconductor strips are over a bulk portion of the semiconductor substrate;
etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate;
forming a liner dielectric layer lining the trench;
forming a buried contact in the trench;
forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips; and
forming isolation regions on opposite sides of the two semiconductor strips, wherein the buried power rail is underlying a portion of the isolation regions.

### Claim 2 (depends on 1)

The method of claim 1, wherein the etching the bulk portion to form the trench comprises:
performing an anisotropic etching to form a portion of the trench extending into the bulk portion; and
performing an isotropic etching to expand the trench, wherein after being expanded, the trench has a diamond-shaped cross-sectional view shape.

### Claim 3 (depends on 1)

The method of claim 1, wherein the forming the buried contact comprises:
forming a seed layer lining the trench, with the seed layer on the liner dielectric layer;
removing a top portion of the seed layer, with a bottom portion of the seed layer remaining; and
plating a conductive material starting from the bottom portion of the seed layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the buried power rail is at a same level as a portion of the two semiconductor strips.

### Claim 5 (depends on 1)

The method of claim 1, wherein the semiconductor substrate comprises:
a first semiconductor layer;
a silicon germanium layer over the first semiconductor layer; and
a second semiconductor layer over the silicon germanium layer, wherein the etching the semiconductor substrate comprises etching the second semiconductor layer and stopping on the silicon germanium layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the etching the bulk portion to form the trench comprises:
etching-through the silicon germanium layer; and
performing an oxidation to oxidize a portion of the silicon germanium layer.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
recessing the isolation regions, wherein top portions of the two semiconductor strips protrude higher than top surfaces of remaining portions of the isolation regions to form a first semiconductor fin and a second conductor fin;
forming a first source/drain region based on the first semiconductor fin; and
forming a contact plug to electrically connect the first source/drain region to the buried power rail and the buried contact.

### Claim 8 (depends on 7)

The method of claim 7, wherein the forming the contact plug comprises:
etching the portion of the isolation regions to form a contact opening, wherein the buried power rail is exposed to the contact opening; and
filling the contact opening to form the contact plug.

### Claim 9 (depends on 7)

The method of claim 7, wherein the top surfaces of the remaining portions of the isolation regions are higher than a top surface of the buried power rail.

### Claim 10

A method of forming an integrated circuit structure, the method comprising:
etching a semiconductor substrate to form two semiconductor strips, wherein the two semiconductor strips are over a bulk portion of the semiconductor substrate;
etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate, wherein the trench comprises a first portion laterally between the two semiconductor strips, and second portions overlapped by the two semiconductor strips;
forming a liner dielectric layer lining the trench;
forming a buried contact in the trench;
forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips; and
forming isolation regions on opposite sides of the two semiconductor strips, wherein the buried power rail is underlying a portion of the isolation regions.

### Claim 11 (depends on 10)

The method of claim 10, wherein the etching the bulk portion to form the trench comprises:
performing a first etching process to form the trench having straight-and-vertical sidewalls; and
performing a second etching process to expand a bottom portion of the trench, wherein after being expanded, the trench has slanted sidewalls.

### Claim 12 (depends on 10)

The method of claim 10, wherein the buried power rail comprises tungsten.

### Claim 13 (depends on 10)

The method of claim 10, wherein the forming the buried contact comprises:
forming a metal seed layer lining the trench;
removing a top portion of the metal seed layer, with a bottom portion of the metal seed layer remaining;
and plating a conductive material starting from the bottom portion of the metal seed layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the removing the top portion of the metal seed layer comprises:
filling a sacrificial material into the trench;
etching back the sacrificial material to a level where the top portion joins the bottom portion of the metal seed layer;
etching the metal seed layer using the sacrificial material as an etching mask; and
removing the sacrificial material.

### Claim 15 (depends on 10)

The method of claim 10 further comprising:
recessing the isolation regions, wherein top portions of the two semiconductor strips protrude higher than top surfaces of remaining portions of the isolation regions to form a first semiconductor fin and a second conductor fin;
forming a first source/drain region based on the first semiconductor fin; and
forming a contact plug to electrically connect the first source/drain region to the buried power rail and the buried contact.

### Claim 16 (depends on 15)

The method of claim 15, wherein the top surfaces of the remaining portions of the isolation regions are higher than a top surface of the buried power rail.

### Claim 17 (depends on 15)

The method of claim 15, wherein the trench has slanted-and-straight edges.

### Claim 18

A method of forming an integrated circuit structure, the method comprising:
etching a semiconductor substrate from a front side to form two semiconductor strips, wherein the two semiconductor strips are over a bulk portion of the semiconductor substrate;
etching the bulk portion to form a trench in the bulk portion of the semiconductor substrate;
forming a liner dielectric layer lining the trench;
depositing a buried contact in the trench;
forming a buried power rail over and connected to the buried contact, wherein the buried power rail is between the two semiconductor strips;
forming isolation regions on opposite sides of the two semiconductor strips, wherein the buried power rail is underlying a portion of the isolation regions; and
forming a contact plug from a backside of the semiconductor substrate, wherein the contact plug is electrically connected to the buried contact.

### Claim 19 (depends on 18)

The method of claim 18, wherein the forming the contact plug comprises:
etching the semiconductor substrate from the backside to form a contact opening, until the buried contact is exposed; and
filling a conductive material into the contact opening.

### Claim 20 (depends on 19)

The method of claim 19 further comprising, after the buried contact is exposed and before the filling the conductive material, removing a bottom portion of the contact plug.