# US 10,872,817 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 10,872,817 B2
- Document ID: US10872817B2
- Status: Granted
- Kind: B2
- Application number: 16/022,965
- Filed: 2018-06-29
- Published: 2019-06-06
- Granted: 2020-12-22
- Earliest claimed: 2017-12-01
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Daeho Yoon; Daeseon Jeon; Jaeyoung Choi
- Web page: https://patentgrep.com/patent/US10872817B2

## CPC

- H10W 20/067: {by modifying the pattern of conductive parts}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- H10D 89/10: Integrated device layouts
- H10W 20/01: {Manufacture or treatment}
- H10W 20/43: Layouts of interconnections
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
providing a layout comprising a first group and a second group, the first group including a first pattern and a second pattern, the second group including a third pattern and a fourth pattern;
examining a bridge risk region in the layout;
biasing one end of at least one of the first and third patterns; and
forming first to fourth conductive patterns by using the first to fourth patterns of the layout, respectively,
wherein the one end of at least one of the first and third patterns is adjacent to the bridge risk region.

### Claim 2 (depends on 1)

The method of claim 1, wherein
the first to fourth patterns extend in parallel to each other in a first direction, and
the one end of at least one of the first and third patterns is adjacent to the bridge risk region in a second direction crossing the first direction.

### Claim 3 (depends on 1)

The method of claim 1, wherein examining the bridge risk region comprises:
defining a first bulging region on one side of the second pattern, based on one end of the first pattern;
defining a second bulging region on one side of the fourth pattern, based on one end of the third pattern; and
defining the bridge risk region that indicates an area where the first bulging region and the second bulging region overlap.

### Claim 4 (depends on 3)

The method of claim 3, wherein, after biasing, the first bulging region and the second bulging region are spaced apart from each other.

### Claim 5 (depends on 3)

The method of claim 3, wherein
a first extension is formed on one side of the second conductive pattern, the first extension corresponding to the first bulging region, and
a second extension is formed on one side of the fourth conductive pattern, the second extension corresponding to the second bulging region.

### Claim 6 (depends on 1)

The method of claim 1, wherein biasing comprises placing an extension pattern on the one end of at least one of the first and third patterns.

### Claim 7 (depends on 1)

The method of claim 1, wherein biasing comprises removing a portion of at least one of the first and third patterns.

### Claim 8 (depends on 1)

The method of claim 1, wherein, after biasing, further comprising performing a design rule check on the layout.

### Claim 9 (depends on 1)

The method of claim 1, wherein neighboring ones of the first to fourth patterns are arranged at substantially the same pitch.

### Claim 10 (depends on 1)

The method of claim 1, wherein
the fourth pattern is disposed between the first and second patterns, and
the second pattern is disposed between the third and fourth patterns.

### Claim 11 (depends on 1)

The method of claim 1, wherein forming the first to fourth conductive patterns comprises:
using the first group of the layout to fabricate a first photomask;
using the second group of the layout to fabricate a second photomask;
using the first photomask to perform a first photolithography process on a substrate; and
using the second photomask to perform a second photolithography process on the substrate.

### Claim 12

A method of manufacturing a semiconductor device, the method comprising:
providing a layout;
performing a line-end biasing on the layout; and
using the layout to form conductive patterns on a substrate,
wherein performing the line-end biasing comprises:
examining a bridge risk region in the layout;
biasing one end of at least one of patterns in the layout, the one end being adjacent to the bridge risk region; and
performing a design rule check.

### Claim 13 (depends on 12)

The method of claim 12, wherein the line-end biasing is repeatedly performed.

### Claim 14 (depends on 12)

The method of claim 12, wherein a first pattern of the biased patterns violates a design rule,
wherein performing the line-end biasing further comprises cancelling the biasing performed on the first pattern.

### Claim 15 (depends on 12)

The method of claim 12, wherein performing the line-end biasing comprises placing an extension pattern on the one end of at least one of patterns.

### Claim 16 (depends on 12)

The method of claim 12, wherein
the patterns in the layout extend in parallel to each other in a first direction, and
the one end of at least one of patterns is adjacent to the bridge risk region in a second direction crossing the first direction.

### Claim 17

A method of manufacturing a semiconductor device, the method comprising:
providing a layout including a first pattern, a second pattern, a third pattern and a fourth pattern that are sequentially arranged in a first direction, the first and third patterns constituting a first group, the second and fourth patterns constituting a second group, the first pattern having a first end, the fourth pattern having a second end;
generating a first bulging region on one side of the third pattern aligned with the first end in the first direction;
generating a second bulging region on one side of the second pattern aligned with the second end in the first direction;
defining a bridge risk region on an area where the first bulging region and the second bulging region overlap;
biasing at least one of the first and second ends of the first and fourth patterns, the at least one end of the first and second ends of the first and fourth patterns being adjacent to the bridge risk region; and
forming first to fourth conductive patterns by using the first to fourth patterns of the layout, respectively.

### Claim 18 (depends on 17)

The method of claim 17, wherein the bridge risk region indicates a zone where an electrical short occurs between the second conductive pattern and the third conductive pattern.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first to fourth patterns extend in parallel to each other in a second direction crossing the first direction.

### Claim 20 (depends on 17)

The method of claim 17, wherein, after biasing, the first bulging region and the second bulging region are spaced apart from each other.