# US 10,872,815 B2 · Conductive interconnect structures in integrated circuits

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- Number: US 10,872,815 B2
- Document ID: US10872815B2
- Status: Granted
- Kind: B2
- Application number: 16/858,838
- Filed: 2020-04-27
- Published: 2020-08-13
- Granted: 2020-12-22
- Earliest claimed: 2018-09-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Jung-Tang Wu; Shao Tzu Lien; Chi-Hung Liao; Szu-Hua Wu; Liang-Yueh Ou Yang; Chin-Szu Lee
- Web page: https://patentgrep.com/patent/US10872815B2

## CPC

- H10W 20/043: {for electroplating}
- H01J 37/32357: {Generation remote from the workpiece, e.g. down-stream}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 72/0416: {with the semiconductor substrates being dipped in baths or vessels}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/052: {by treatments not introducing additional elements therein}
- H10W 20/0523: {by irradiating with ultraviolet or particle radiation}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/0112: {using conductive layers comprising silicides}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming a dielectric layer over a substrate;
forming an opening in the dielectric layer;
depositing a conductive seed layer along sidewalls and a bottom of the opening, wherein an oxide layer is formed on the conductive seed layer;
performing a reactive remote plasma surface treatment to expose the oxide layer to a reducing agent and to remove at least a portion of the oxide layer; and
after performing the reactive remote plasma surface treatment, electroplating a conductive layer on the conductive seed layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the reducing agent is hydrogen radicals.

### Claim 3 (depends on 1)

The method of claim 1, wherein performing the reactive remote plasma surface treatment and the electroplating are performed in a same cluster tool.

### Claim 4 (depends on 1)

The method of claim 1 further comprising, after performing the reactive remote plasma surface treatment and prior to electroplating, performing a soak in an electrolyte bath, wherein the substrate remains in the electrolyte bath during electroplating.

### Claim 5 (depends on 4)

The method of claim 4, wherein the electrolyte bath comprises CoSO4.7H2O, citric acid, hydrochloric acid, and a Co suppressor.

### Claim 6 (depends on 5)

The method of claim 5, wherein soaking the substrate in the electrolyte bath is performed for a time period from about 0.75 seconds to about 100 seconds prior to applying an electroplating current.

### Claim 7 (depends on 1)

The method of claim 1, wherein the reactive remote plasma surface treatment smoothes an exposed surface.

### Claim 8 (depends on 1)

The method of claim 1, wherein the reactive remote plasma surface treatment makes an exposed surface more hydrophilic.

### Claim 9

A method of forming a semiconductor device, the method comprising:
forming a conductive feature on a substrate;
depositing a conductive seed layer over the conductive feature, wherein an oxide layer is formed over a surface of the conductive seed layer;
performing a remote plasma surface treatment to expose the oxide layer to a reducing agent, the remote plasma surface treatment reducing a first amount of the oxide layer;
after performing the remote plasma surface treatment, performing a soak in a chemical bath, the soak in the chemical bath reducing a second amount of the oxide layer; and
electroplating a conductive layer over the conductive seed layer, wherein performing the remote plasma surface treatment, performing the soak, and electroplating are performed in a same cluster tool without exposing the substrate to an oxygen-containing environment.

### Claim 10 (depends on 9)

The method of claim 9, wherein the substrate remains in the chemical bath while electroplating the conductive layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein an open circuit potential is less than 0.1 volt prior to electroplating.

### Claim 12 (depends on 9)

The method of claim 9, wherein the electroplating comprises a ramp-up period, a first plating period, and a second plating period, wherein an electroplating current is increased during the ramp-up period, the electroplating current is set at a first current during the first plating period, and the electroplating current is set at a second current during the second plating period, the second current being greater than the first current.

### Claim 13 (depends on 12)

The method of claim 12, wherein the first current is higher than a highest current level at an end of the ramp-up period.

### Claim 14 (depends on 9)

The method of claim 9, wherein the remote plasma surface treatment exposes the oxide layer to hydrogen radicals.

### Claim 15 (depends on 9)

The method of claim 9 further comprising, prior to forming the conductive seed layer:
forming a barrier layer over the conductive feature, wherein the conductive seed layer is formed on the barrier layer.

### Claim 16 (depends on 15)

The method of claim 15 further comprising, prior to forming the barrier layer:
forming a metal-containing layer over the conductive feature, wherein the conductive feature is a semiconductor material; and
annealing to react the metal-containing layer with the semiconductor material.

### Claim 17

A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a source/drain region;
forming an opening through the first dielectric layer to the source/drain region;
forming a silicide region in the source/drain region exposed in the opening;
forming a first conductive layer in the opening;
exposing the first conductive layer to an oxygen-containing environment, the exposing forming an oxide layer on the first conductive layer;
reducing at least a first portion of the oxide layer using a plasma process;
reducing at least a second portion of the oxide layer using a wet process; and
electroplating a second conductive layer over the first conductive layer, wherein the exposing, the plasma process, the wet process, and the electroplating are performed in a single cluster tool.

### Claim 18 (depends on 17)

The method of claim 17, wherein the plasma process is a reactive remote plasma process generating hydrogen radicals.

### Claim 19 (depends on 18)

The method of claim 18, wherein the plasma process uses a process gas of H2 or NH3, and a carrier gas of Ar or N2.

### Claim 20 (depends on 18)

The method of claim 18, wherein the wet process and the electroplating are performed in a same chemical bath.