# US 10,872,811 B2 · Memory device and manufacturing method thereof

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- Number: US 10,872,811 B2
- Document ID: US10872811B2
- Status: Granted
- Kind: B2
- Application number: 16/365,681
- Filed: 2019-03-27
- Published: 2020-10-01
- Granted: 2020-12-22
- Earliest claimed: 2019-03-27
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Huang-Nan Chen
- Web page: https://patentgrep.com/patent/US10872811B2

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/46: comprising air gaps
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 12/482: {Bit lines}
- H10B 12/488: {Word lines}
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/6334: {using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 50/667: {by liquid etching only}
- H10P 95/062: {involving a dielectric removal step}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/092: {by smoothing the dielectric parts}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4451: {Semiconductor materials, e.g. polysilicon}
- H10W 20/48: Insulating materials thereof
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a memory device including a substrate, a plurality of contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The contacts are respectively disposed on ends of the active areas. The air gaps respectively surround the sidewalls of the contacts.

## Claims

### Claim 1

A manufacturing method of a memory device, comprising:
providing a substrate, wherein the substrate has a plurality of first regions and a plurality of second regions;
forming a plurality of word line sets in the first regions;
forming a first dielectric layer on the substrate of the first regions;
forming a conductive layer on the substrate of the second regions, wherein a top surface of the conductive layer is lower than a top surface of the first dielectric layer;
forming a sacrificial layer to surround the conductive layer;
conformally forming a second dielectric layer on the substrate;
performing an etching process to form openings in the conductive layer and the second dielectric layer of the second regions, wherein the openings expose a first isolation structure in the substrate of the second regions;
forming a second isolation structure in the openings;
performing a planarization process to expose the sacrificial layer;
recessing a portion of the conductive layer to form a first conductive structure and expose the sacrificial layer;
removing the sacrificial layer to form an air gap surrounding an upper portion of the first conductive structure; and
forming a second conductive structure on the first conductive structure to encapsulate the air gap.

### Claim 2 (depends on 1)

The manufacturing method of the memory device of claim 1, wherein the forming the sacrificial layer to surround the conductive layer comprises:
forming a first conductive material on the substrate of the second regions;
forming a sacrificial material to conformally cover the first conductive material and the first dielectric layer;
removing a portion of the sacrificial material to form the sacrificial layer and expose a top surface of the first conductive material and the top surface of the first dielectric layer; and
forming a second conductive material on the first conductive material, such that the sacrificial layer surrounds sidewalls of the second conductive material.

### Claim 3 (depends on 1)

The manufacturing method of the memory device of claim 1, wherein after the second dielectric layer is formed, the second dielectric layer has an uneven top surface, and a top surface of the second dielectric layer of the second regions is lower than a top surface of the second dielectric layer of the first regions.

### Claim 4 (depends on 1)

The manufacturing method of the memory device of claim 1, wherein a portion of the second dielectric layer of the first regions is further removed to expose the top surface of the first dielectric layer during the etching process.

### Claim 5 (depends on 1)

The manufacturing method of the memory device of claim 1, wherein the second isolation structure is in contact with the first isolation structure and separates the conductive layer and the sacrificial layer on the second regions.

### Claim 6

A manufacturing method of a memory device, comprising:
providing a substrate, wherein the substrate has a plurality of active areas;
forming a first dielectric layer on the substrate;
forming a plurality of contact openings in the first dielectric layer, wherein the contact openings are respectively disposed on ends of the active areas;
respectively forming a plurality of conductive layers in the contact openings;
forming a sacrificial layer to surround the conductive layers;
recessing a portion of the conductive layers to form first conductive structures, wherein the first conductive structures include lower portions and upper portions on the lower portions, and a bottom width of the lower portions is greater than a bottom width of the upper portions;
removing the sacrificial layer to form air gaps surrounding the upper portions of the first conductive structures; and
forming second conductive structures on the first conductive structures to encapsulate the air gaps,
wherein the air gaps are in direct contact with the upper portions of the first conductive structures after the forming the second conductive structures on the first conductive structures.

### Claim 7 (depends on 6)

The manufacturing method of the memory device of claim 6, wherein the forming the sacrificial layer to surround the conductive layers comprises:
forming a first conductive material in the contact openings;
forming a sacrificial material to conformally cover the first conductive material and the first dielectric layer;
removing a portion of the sacrificial material to form the sacrificial layer and expose a top surface of the first conductive material and a top surface of the first dielectric layer; and
forming a second conductive material on the first conductive material, such that the sacrificial layer surrounds sidewalls of the second conductive material.

### Claim 8 (depends on 7)

The manufacturing method of the memory device of claim 7, wherein after the sacrificial layer is completely removed, the air gaps completely surround the upper portions of the first conductive structures.