# US 10,872,810 B2 · Fin field effect transistor device structure and method for forming the same

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- Number: US 10,872,810 B2
- Document ID: US10872810B2
- Status: Granted
- Kind: B2
- Application number: 16/353,421
- Filed: 2019-03-14
- Published: 2020-09-17
- Granted: 2020-12-22
- Earliest claimed: 2019-03-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Lin-Yu Huang; Jia-Chuan You; Chia-Hao Chang; Tien-Lu Lin; Yu-Ming Lin; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US10872810B2

## CPC

- H10W 20/46: comprising air gaps
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/076: {in via holes or trenches}
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for forming a fin field effect transistor device structure includes forming fin structures over a substrate. The method also includes forming a gate structure across the fin structures. The method also includes forming source/drain epitaxial structures over the fin structures. The method also includes forming blocking structures between the source/drain epitaxial structures. The method also includes depositing contact structures over the source/drain epitaxial structures and between the blocking structures. The method also includes removing a top portion of the blocking structures. The method also includes depositing an etch stop layer over the blocking structures and the contact structures, so that an air gap is formed between the etch stop layer and the blocking structure.

## Claims

### Claim 1

A method for forming a fin field effect transistor device structure, comprising:
forming fin structures over a substrate;
forming a gate structure across the fin structures;
forming source/drain epitaxial structures over the fin structures;
forming blocking structures between the source/drain epitaxial structures;
depositing contact structures over the source/drain epitaxial structures and between the blocking structures;
removing a top portion of the blocking structures; and
depositing an etch stop layer over the blocking structures and the contact structures, wherein an air gap is formed between the etch stop layer and the blocking structure, and wherein the etch stop layer and the blocking structure are separated by the air gap.

### Claim 2 (depends on 1)

The method for forming the fin field effect transistor device structure as claimed in claim 1, further comprising:
forming a liner layer over sidewalls of the blocking structures before depositing the contact structure.

### Claim 3 (depends on 1)

The method for forming the fin field effect transistor device structure as claimed in claim 1, further comprising:
removing a top portion of the contact structures; and
forming a cap layer over the contact structures.

### Claim 4 (depends on 1)

The method for forming the fin field effect transistor device structure as claimed in claim 1, wherein forming the blocking structures comprises:
forming a dielectric layer surrounding the source/drain epitaxial structures;
removing a portion of the dielectric layer between the source/drain epitaxial structures;
filling a blocking material between the source/drain epitaxial structures; and
removing the dielectric layer over the source/drain epitaxial structures to form trenches,
wherein the contact structures are formed in the trenches and the dielectric layer is remain over sidewalls of the blocking material.

### Claim 5 (depends on 4)

The method for forming the fin field effect transistor device structure as claimed in claim 4, wherein a bottom portion the dielectric layer is left between the source/drain epitaxial structures.

### Claim 6 (depends on 4)

The method for forming the fin field effect transistor device structure as claimed in claim 4, wherein the blocking structures and the source/drain epitaxial structures are separated by the dielectric layer.

### Claim 7 (depends on 1)

The method for forming the fin field effect transistor device structure as claimed in claim 1, further comprising:
removing remaining portions of the blocking structures.

### Claim 8 (depends on 1)

The method for forming the fin field effect transistor device structure as claimed in claim 1, wherein the source/drain epitaxial structures are surrounded by the contact structures.

### Claim 9

A method for forming a fin field effect transistor device structure, comprising:
forming fin structures over a substrate;
forming a gate structure across the fin structures;
forming source/drain epitaxial structures over the fin structures on opposite sides of the gate structure;
forming a dielectric structure surrounding the source/drain epitaxial structures;
forming blocking structures between the fin structures;
depositing contact structures over the fin structures;
forming a via structure over a top surface of the contact structure and electrically connected to the contact structures;
removing a top portion of the blocking structures; and
depositing an etch stop layer over the blocking structures, the contact structures, and the via structure, wherein an air gap is formed between the contact structures; and
planarizing the etch stop layer to expose the via structure.

### Claim 10 (depends on 9)

The method for forming the fin field effect transistor device structure as claimed in claim 9, further comprising:
forming a dielectric layer over sidewalls of the blocking structures.

### Claim 11 (depends on 10)

The method for forming the fin field effect transistor device structure as claimed in claim 10, wherein an angle between a sidewall of the dielectric layer and a bottom surface of the dielectric layer is in a range from about 70° to about 89°.

### Claim 12 (depends on 10)

The method for forming the fin field effect transistor device structure as claimed in claim 10, further comprising:
forming a dielectric cap layer over the contact structures,
wherein the dielectric cap layer and the dielectric layer are made of different materials.

### Claim 13 (depends on 9)

The method for forming the fin field effect transistor device structure as claimed in claim 9, further comprising:
depositing a sacrificial etch stop layer over the blocking structures and the contact structures;
depositing a hard mask layer over the sacrificial etch stop layer before forming the via structure; and
removing the sacrificial etch stop layer and the hard mask layer after forming the via structure.

### Claim 14 (depends on 13)

The method for forming the fin field effect transistor device structure as claimed in claim 13, wherein the sacrificial etch stop layer and the hard mask layer are made of different materials.

### Claim 15

A method for forming a fin field effect transistor device structure, comprising:
forming a first fin structure and a second fin structure over a substrate;
forming a gate structure across the first fin structure and the second fin structure;
growing a first source/drain epitaxial structure over the first fin structure and a second source/drain epitaxial structure over the second fin structure over opposite sides of the gate structure;
depositing a dielectric layer covering the first source/drain epitaxial structure and the second source/drain epitaxial structure;
forming a blocking structure between the first source/drain epitaxial structure and the second source/drain epitaxial structure;
removing the dielectric layer over the first source/drain epitaxial structure and the second source/drain epitaxial structure to expose the first source/drain epitaxial structure and the second source/drain epitaxial structure;
forming a first contact structure over the first source/drain epitaxial structure and a second contact structure over the second source/drain epitaxial structure;
recessing the blocking structure between the first source/drain epitaxial structure and the second source/drain epitaxial structure;
depositing an etching stop layer over the first contact structure, the second contact structure, and the blocking structure;
forming a hard mask layer formed over the etching stop layer; and
forming a via structure through the hard mask layer and the etching stop layer,
wherein an air gap is formed below the etching stop layer and between the first contact structure and the second contact structure, and wherein the via structure is in direct contact with the first contact structure.

### Claim 16 (depends on 15)

The method for forming the fin field effect transistor device structure as claimed in claim 15, further comprising:
forming a liner layer over sidewalls of the first contact structure and the second contact structure,
wherein the liner layer and the dielectric layer are made of different materials.

### Claim 17 (depends on 16)

The method for forming the fin field effect transistor device structure as claimed in claim 16, wherein after removing the dielectric layer, the dielectric layer remains over the liner layer.

### Claim 18 (depends on 15)

The method for forming the fin field effect transistor device structure as claimed in claim 15, wherein the dielectric layer between the first source/drain epitaxial structure and the second source/drain epitaxial structure is partially removed.

### Claim 19 (depends on 18)

The method for forming the fin field effect transistor device structure as claimed in claim 18, wherein a bottom surface of the blocking layer is higher than a bottom surface of the first contact structure.

### Claim 20 (depends on 15)

The method for forming the fin field effect transistor device structure as claimed in claim 15, wherein the blocking structure between the first source/drain epitaxial structure and the second source/drain epitaxial structure is further recessed until the dielectric layer is exposed.