# US 10,872,809 B2 · Contact structures for integrated circuit products

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- Number: US 10,872,809 B2
- Document ID: US10872809B2
- Status: Granted
- Kind: B2
- Application number: 16/579,035
- Filed: 2019-09-23
- Published: 2020-01-16
- Granted: 2020-12-22
- Earliest claimed: 2017-12-11
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Ruilong Xie; Lars W. Liebmann; Balasubramanian Pranatharthi Haran; Veeraraghavan Basker
- Web page: https://patentgrep.com/patent/US10872809B2

## CPC

- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/092: {by smoothing the dielectric parts}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

One illustrative transistor device disclosed herein includes a gate structure positioned above at least an active region, wherein the gate structure has an axial length in a direction corresponding to a gate width direction of the transistor device. In this example, a first portion of the axial length of the gate structure has a first upper surface and a second portion of the axial length of the gate structure has a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface. The device also includes a gate contact structure that contacts the first upper surface of the gate structure.

## Claims

### Claim 1

A transistor device, comprising:
a gate structure positioned above at least an active region, the gate structure having an axial length in a direction corresponding to a gate width direction of the transistor device, a first portion of the axial length of the gate structure having a first upper surface and a second portion of the axial length of the gate structure having a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface; and
a gate contact structure that contacts the first upper surface of the gate structure.

### Claim 2 (depends on 1)

The transistor device of claim 1, further comprising:
a source/drain contact structure positioned adjacent the gate structure and conductively coupled to a source/drain region of the transistor device, the source/drain contact structure having an axial length in a direction corresponding to the gate width direction of the transistor device, a first portion of the axial length of the source/drain contact structure having a third upper surface and a second portion of the axial length of the source/drain contact structure having a fourth upper surface, wherein the third upper surface is positioned at a level that is above a level of the fourth upper surface; and
a contact structure that contacts the third upper surface of the source/drain contact structure.

### Claim 3 (depends on 2)

The transistor device of claim 2, wherein the first upper surface and the third upper surface are positioned at approximately the same level.

### Claim 4 (depends on 3)

The transistor device of claim 3, wherein the second upper surface and the fourth upper surface are positioned at approximately the same level.

### Claim 5 (depends on 1)

The transistor device of claim 1, wherein, when viewed from above, the gate contact structure has a substantially rectangular configuration.

### Claim 6 (depends on 1)

The transistor device of claim 1, wherein the gate contact structure is positioned above the active region.

### Claim 7 (depends on 1)

The transistor device of claim 1, further comprising:
at least one layer of insulating material positioned above the gate structure;
an opening in the at least one layer of insulating material; and
an internal sidewall spacer positioned within the opening, wherein a portion of the first surface is exposed within the internal sidewall spacer and wherein the gate contact structure is positioned within the internal sidewall spacer, the internal sidewall spacer laterally surrounding the gate contact structure.

### Claim 8 (depends on 7)

The transistor device of claim 7, wherein the internal sidewall spacer physically contacts and engages the gate contact structure.

### Claim 9

A transistor device, comprising:
a gate structure positioned above at least an active region, the gate structure having an axial length in a direction corresponding to a gate width direction of the transistor device, a first portion of the axial length of the gate structure having a first upper surface and a second portion of the axial length of the gate structure having a second upper surface, wherein the first upper surface is positioned at a level that is above a level of the second upper surface;
a gate contact structure positioned entirely above the active region, the gate contact structure contacting the first upper surface of the gate structure;
a source/drain contact structure positioned adjacent the gate structure and conductively coupled to a source/drain region of the transistor device, the source/drain contact structure having an axial length in a direction corresponding to the gate width direction of the transistor device, a first portion of the axial length of the source/drain contact structure having a third upper surface and a second portion of the axial length of the source/drain contact structure having a fourth upper surface, wherein the third upper surface is positioned at a level that is above a level of the fourth upper surface; and
a contact structure that contacts the third upper surface of the source/drain contact structure.

### Claim 10 (depends on 9)

The transistor device of claim 9, wherein the first upper surface and the third upper surface are positioned at approximately the same level.

### Claim 11 (depends on 10)

The transistor device of claim 10, wherein the second upper surface and the fourth upper surface are positioned at approximately the same level.

### Claim 12 (depends on 10)

The transistor device of claim 10, further comprising:
at least one layer of insulating material positioned above the gate structure;
an opening in the at least one layer of insulating material; and
an internal sidewall spacer positioned within the opening, wherein a portion of the first surface is exposed within the internal sidewall spacer and wherein the gate contact structure is positioned within the internal sidewall spacer, the internal sidewall spacer laterally surrounding the gate contact structure.

### Claim 13 (depends on 12)

The transistor device of claim 12, wherein the internal sidewall spacer physically contacts and engages the gate contact structure.

### Claim 14

A device, comprising:
a gate structure for a transistor device;
at least one layer of insulating material positioned above the gate structure, the at least one layer of insulating material having an opening formed therein and an upper surface that is positioned at a first level;
an internal sidewall spacer positioned within the opening;
a conductive member positioned within the internal sidewall spacer, the conductive member having an axial length and a recessed upper surface that is positioned at a second level that is below the first level;
an insulating contact cap positioned above the recessed upper surface of the conductive member, the insulating contact cap being positioned above a first portion of the axial length of the conductive member while a second portion of the axial length of the conductive member is not covered by the insulating contact cap; and
a gate contact structure that conductively contacts the gate structure, wherein at least a portion of the gate contact structure is positioned vertically above at least one of the internal sidewall spacer or the insulating contact cap.

### Claim 15 (depends on 14)

The device of claim 14, wherein the axial length of the conductive member extends in a direction corresponding to a gate width direction of the transistor device.

### Claim 16 (depends on 14)

The device of claim 14, wherein at least a portion of the gate contact structure physically contacts and engages at least one of the internal sidewall spacer or the insulating contact cap.

### Claim 17 (depends on 14)

The device of claim 14, wherein the conductive member has a bottom surface that is positioned at a level that is above a level of an upper surface of the gate structure.

### Claim 18 (depends on 17)

The device of claim 17, wherein at least a portion of the internal sidewall spacer is positioned vertically above a sidewall spacer positioned adjacent the gate structure.

### Claim 19 (depends on 14)

The device of claim 14, wherein the insulating contact cap has an upper surface that is substantially co-planar with the upper surface of the at least one layer of insulating material.

### Claim 20 (depends on 14)

The device of claim 14, wherein the conductive member is conductively coupled to a source/drain region of the transistor device.