# US 10,872,808 B2 · Semiconductor device and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,808 B2 - Document ID: US10872808B2 - Status: Granted - Kind: B2 - Application number: 16/215,294 - Filed: 2018-12-10 - Published: 2019-10-10 - Granted: 2020-12-22 - Earliest claimed: 2018-04-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jin Ho Park; Sae Il Son; Hye Jun Jin; Yun-Won Ha - Web page: https://patentgrep.com/patent/US10872808B2 ## CPC - H10W 20/085: {involving intermediate temporary filling with material} - H10W 20/076: {in via holes or trenches} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/096: {by contacting with gases, liquids or plasmas} - H10W 20/42: Vias, e.g. via plugs - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An etch stop layer is formed on a lower wiring. An interlayer insulating film covers the lower wiring and the etch stop layer. A via exposes an upper surface of the etch stop layer, in the interlayer insulating film. A first filler is formed in the via. The first filler is etched to a first filler pattern. A second filler is formed on the first filler pattern and is etched to a second filler pattern. A trench is formed by etching the interlayer insulating film. The first and second filler patterns are etched during the forming of the trench to form a residual filler pattern. The residual filler pattern and the etch stop layer are removed and a wiring structure is formed electrically connected to the lower wiring. The via includes lower and upper portions and the trench includes the upper portion of the via. ## Claims ### Claim 1 A method of fabricating a semiconductor device, the method comprising: forming a lower wiring; forming an etch stop layer on the lower wiring; forming an interlayer insulating film covering the lower wiring and the etch stop layer; forming a via in the interlayer insulating film, the via exposing an upper surface of the etch stop layer; forming a first filler in the via, the first filler partially filling the via; etching the first filler to form a first filler pattern; forming a second filler on the first filler pattern within the via, the first filler pattern and the second filler, together, partially filling the via; etching the second filler to form a second filler pattern; etching the interlayer insulating film to form a trench; etching the first and second filler patterns, during the forming of the trench, to form a residual filler pattern; removing the residual filler pattern and the etch stop layer; and forming a wiring structure within the via and the trench, the wiring structure being electrically connected to the lower wiring, wherein the via comprises a lower portion and an upper portion disposed on the lower portion, and wherein the trench comprises the upper portion of the via. ### Claim 2 (depends on 1) The method of claim 1, wherein the first and second fillers comprise a same material. ### Claim 3 (depends on 2) The method of claim 2, wherein the first and second fillers each comprise a bottom anti-reflective coating (BARC). ### Claim 4 (depends on 1) The method of claim 1, wherein the via comprises a first portion filled with the first filler and a second portion not filled with the first filler, and a first damaged region is formed in the interlayer insulating film along sidewalls of the second portion when the first filler is etched. ### Claim 5 (depends on 4) The method of claim 4, wherein the interlayer insulating film comprises the first damaged region aid a first undamaged region which is in contact with the first damaged region, wherein a carbon content of the first damaged region is lower than that of the first undamaged region. ### Claim 6 (depends on 1) The method of claim 1, wherein the forming of the first filler comprises forming a first anti-reflection film on the interlayer insulating film at the same time as forming the first filler. ### Claim 7 (depends on 6) The method of claim 6, wherein the forming of the second filler comprises forming a second anti-reflection film on the interlayer insulating film at the same time as forming the second filler. ### Claim 8 (depends on 7) The method of claim 7, further comprising forming a photoresist on the second anti-reflection film. ### Claim 9 (depends on 8) The method of claim 8, further comprising forming a photoresist pattern by patterning the photoresist. ### Claim 10 (depends on 9) The method of claim 9, wherein the photoresist pattern exposes a portion of an upper surface of the second anti-reflection film. ### Claim 11 A method of fabricating a semiconductor device, the method comprising: forming a lower wiring; forming an etch stop layer on the lower wiring; forming an interlayer insulating film covering the lower wiring and the etch stop layer; forming a via in the interlayer insulating film, the via exposing an upper surface of the etch stop layer; forming a first filler in the via; etching the first filler to form a first filler pattern; forming a second filler on the first filler pattern within the via; etching the second filler to form a second filler pattern; forming a third filler on the second filler pattern within the via; etching the third filler to form a third filler pattern; etching the interlayer insulating film to form a trench; etching the first, second and third filler patterns, during the forming of the trench, to form a residual filler pattern; removing the residual filler pattern and the etch stop layer; and forming a wiring structure within the via and the trench, the wiring structurre being electrically connected to the lower wiring, wherein the via comprises a lower portion and an upper portion disposed on the lower portion, and wherein the trench comprises the upper portion of the via. ### Claim 12 A method fabricating a semiconductor device, the method comprising: forming a lower wiring; forming an etch stop layer on the lower wiring; forming an interlayer insulating film coveting the lower wiring and the etch stop layer; forming a via in the interlayer insulating film, the via exposing an upper surface of the etch stop layer; forming a first filler in the via; etching the first filler to form a first filler pattern; forming a second filler on the first filler pattern within the via; etching the second filler to form a second filler pattern; etching the interlayer insulating film to form a trench; etching the first and second filler patterns, during the forming of the trench, to form a residual filler pattern; removing the residual filler pattern and the etch stop layer; and forming a wiring structure within the via and the trench, the wiring structure being electrically connected to the lower wiring, wherein the via comprises a lower portion and an upper portion disposed on the lower portion, wherein the trench comprises the upper portion of the via, wherein the via comprises a first portion filled with the first filler and a second portion not filled with the first filler, and a first damaged region is formed in the interlayer insulating film along sidewalls of the second portion when the first filler is etched, and wherein the via comprises a third portion filled with the second filler and a fourth portion not filled with the second filler, the third portion is a part of the first portion, and a second damaged region is formed in the interlayer insulating film along sidewalls of the fourth portion when the second filler is etched. ### Claim 13 (depends on 12) The method of claim 12, further comprising: forming a third filler on the second filler pattern within the via; and etching the third filler to form a third filler pattern, wherein the first through third filler patterns are etched to form the residual filler pattern. ### Claim 14 (depends on 12) The method of claim 12, wherein the first and second fillers comprise a same material. ### Claim 15 (depends on 14) The method of claim 14, wherein the first and second fillers each corm rise a bottom anti-reflective coating (BARC). ### Claim 16 (depends on 12) The method of claim 12, wherein a carbon content of the second damaged region is lower than that of the first damaged region. ### Claim 17 (depends on 12) The method of claim 12, Wherein the interlayer insulating film comprises the first damaged region and a first undamaged region which is in contact with the first damaged region, wherein a carbon content of the first damaged region is lower than that of the first undamaged region. ### Claim 18 (depends on 12) The method of claim 12, wherein the forming of the first filler comprises forming a first anti-reflection film on the interlayer insulating film at the same time as forming the first filler. ### Claim 19 (depends on 18) The method of claim 18, wherein the forming of the second filler comprises forming a second anti-reflection film on the interlayer insulating film at the same time as forming the second filler. ### Claim 20 (depends on 19) The method of claim 19, further comprising: forming a photoresist on the second anti-reflection film; and forming a photoresist pattern by patterning the photoresist, wherein the photoresist pattern exposes a portion of an upper surface of the second anti-reflection film.