# US 10,872,806 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,872,806 B2
- Document ID: US10872806B2
- Status: Granted
- Kind: B2
- Application number: 16/235,808
- Filed: 2018-12-28
- Published: 2019-05-09
- Granted: 2020-12-22
- Earliest claimed: 2016-01-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Chun Huang; Chih-Hsiang Yao; Jye-Yen Cheng
- Web page: https://patentgrep.com/patent/US10872806B2

## CPC

- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/43: Layouts of interconnections
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4432: {the principal metal being a noble metal, e.g. gold}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/48: Insulating materials thereof
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.

## Claims

### Claim 1

A semiconductor device, comprising:
a pair of spaced-apart metal wirings disposed in a first dielectric layer;
a second dielectric layer disposed over a portion of the first dielectric layer;
a third dielectric layer disposed over the plurality of metal wirings and between each of the pair of metal wirings;
a barrier layer in contact with and surrounding each of the pair of metal wirings; and
a fourth dielectric layer disposed over the pair of metal wirings,
wherein the second dielectric layer is disposed between and in contact with the barrier layer and the third dielectric layer, and
a portion of the fourth dielectric layer is disposed between portions of the third dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the barrier layer is in contact with the first dielectric layer and the third dielectric layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein an upper portion of the third dielectric layer is above the second dielectric layer and a lower portion of the third dielectric layer is below the second dielectric layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the lower portion of the third dielectric layer is surrounded by the first dielectric layer.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein:
the third dielectric layer comprises a first sidewall and a second sidewall,
the first sidewall and the second sidewall are spaced-apart, and
the first and second sidewalls connect the upper portion of the third dielectric layer to the lower portion of the third dielectric layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a second pair of spaced-apart wirings disposed in the fourth dielectric layer.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a thickness of the third dielectric layer is in a range of 10 Å to 100 Å.

### Claim 8

A semiconductor device, comprising:
a pair of spaced-apart metal wirings disposed in a first dielectric layer;
a second dielectric layer disposed over a portion of the first dielectric layer;
a third dielectric layer disposed over the plurality of metal wirings and between each of the pair of metal wirings; and
a barrier layer in contact with and surrounding each of the pair of metal wirings;
wherein the second dielectric layer is disposed between the barrier layer and the third dielectric layer, and
the third dielectric layer is in direct contact with the second dielectric layer, the barrier layer, and each of the pair of metal wirings.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the third dielectric layer comprises an upper portion and a lower portion, the upper portion being above the second dielectric layer and the lower portion being below the second dielectric layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the lower portion is surrounded by the first dielectric layer.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein a portion of the third dielectric layer between the pair of metal wirings comprises a first sidewall and a second sidewall with a recess between the first sidewall and the second sidewall.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising:
a fourth dielectric layer disposed over the third dielectric layer; and
a second pair of spaced-apart wirings disposed in the fourth dielectric layer.

### Claim 13 (depends on 8)

The semiconductor device of claim 8, wherein a thickness of the third dielectric layer is in a range of 10 Å to 100 Å.

### Claim 14

A semiconductor device, comprising:
a pair of spaced-apart metal wirings disposed in a first dielectric layer;
a second dielectric layer disposed over a portion of the first dielectric layer;
a third dielectric layer disposed over the plurality of metal wirings and between each of the pair of metal wirings; and
a fourth dielectric layer disposed over the third dielectric layer,
wherein a portion of the fourth dielectric layer is disposed in the first dielectric layer between the pair of metal wirings and a depth of the fourth dielectric layer in the first dielectric layer is greater than a depth of the second dielectric layer in the first dielectric layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising a barrier layer between the pair of metal wirings and the first dielectric layer, the barrier layer being in contact with the first dielectric layer, the second dielectric layer, and the third dielectric layer.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the fourth dielectric layer comprises an upper portion and a lower portion, and the lower portion is surrounded by the third dielectric layer.

### Claim 17 (depends on 14)

The semiconductor device of claim 14, wherein the third dielectric layer comprises an upper portion and a lower portion, the upper portion being above the second dielectric layer and the lower portion being below the second dielectric layer.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein:
the third dielectric layer further comprises a first sidewall and a second sidewall spaced-apart from the first sidewall, and
the first sidewall and the second sidewall connect the upper portion to the lower portion.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, further comprising a second pair of spaced-apart wirings disposed in the fourth dielectric layer.

### Claim 20 (depends on 14)

The semiconductor device of claim 14, wherein a thickness of the third dielectric layer is in a range of 10 Å to 100 Å.