# US 10,872,805 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,872,805 B2
- Document ID: US10872805B2
- Status: Granted
- Kind: B2
- Application number: 16/208,333
- Filed: 2018-12-03
- Published: 2020-04-02
- Granted: 2020-12-22
- Earliest claimed: 2018-09-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuei-Ming Chang; Chi-Wei Wu; Yi-Chieh Hsieh
- Web page: https://patentgrep.com/patent/US10872805B2

## CPC

- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a substrate, a shallow trench isolation (STI) structure, a first source/drain, a second source/drain, and an isolation dielectric. The substrate has a semiconductor fin. The STI structure surrounds the semiconductor fin. The first source/drain is embedded in the semiconductor fin. The second source/drain is embedded in the semiconductor fin. The isolation dielectric is between the first and second source/drains and extending into the semiconductor fin. An upper surface of the STI structure is free from coverage of the isolation dielectric.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a semiconductor fin;
a shallow trench isolation (STI) structure surrounding the semiconductor fin;
a first source/drain embedded in the semiconductor fin;
a second source/drain embedded in the semiconductor fin; and
an isolation dielectric between the first and second source/drains and extending into the semiconductor fin, wherein an upper surface of the STI structure is free from coverage of the isolation dielectric.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a bottom of the isolation dielectric is lower than a top surface of the STI structure.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the isolation dielectric is in contact with the substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the isolation dielectric runs through the semiconductor fin from above the semiconductor fin to the substrate.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the isolation dielectric is separated from the first and second source/drains.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the substrate has a first portion under the isolation dielectric and a second portion adjacent to the isolation dielectric, and a top surface of the first portion is lower than a top surface of the second portion.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first spacer over the semiconductor fin and in contact with the isolation dielectric.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further comprising:
a second spacer over the semiconductor fin, wherein the isolation dielectric is between the first and second spacers.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate stack over the semiconductor fin and having a top surface substantially level with a top surface of the isolation dielectric.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising:
an insulating fin on the substrate, parallel to the semiconductor fin, and between the isolation dielectric and the semiconductor fin.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, further comprising:
an insulating fin on the substrate and parallel to the semiconductor fin, wherein the isolation dielectric is in contact with a top surface of the insulating fin.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, further comprising:
an insulating fin on the substrate and parallel to the semiconductor fin, wherein a bottom of the isolation dielectric is lower a bottom of the insulating fin.

### Claim 13

A semiconductor device, comprising:
a substrate having a first semiconductor fin;
a shallow trench isolation (STI) structure surrounding the first semiconductor fin;
a first source/drain embedded in the first semiconductor fin;
a second source/drain embedded in the first semiconductor fin; and
an isolation dielectric between the first and second source/drains, extending into the first semiconductor fin, and in contact with a sidewall of the STI structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein a bottom of the isolation dielectric is lower than a top surface of the STI structure.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein a bottom of the isolation dielectric is lower than a bottom of the first semiconductor fin.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein the substrate further has a second semiconductor fin parallel to the first semiconductor fin and in contact with the isolation dielectric.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein the substrate further has a second semiconductor fin parallel to the first semiconductor fin, wherein the semiconductor device further comprises a gate stack straddling the second semiconductor fin and in contact with the isolation dielectric.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a hard mask over the gate stack and having a top surface substantially level with a top surface of the isolation dielectric.

### Claim 19

A semiconductor device, comprising:
a substrate;
a semiconductor fin on the substrate;
an isolation structure surrounding the semiconductor fin;
a gate structure straddling the semiconductor fin;
a dielectric fin partially embedded in the isolation structure, projecting upwardly above the isolation structure, and in contact with a longitudinal end of the gate structure; and
a dielectric plug partially embedded in the substrate, landing on the dielectric fin, and in contact with the longitudinal end of the gate structure, wherein a bottommost portion of the dielectric plug is lower than a top surface of the substrate.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, further comprising:
a hard mask layer over the gate structure, wherein the dielectric plug is in contact with a longitudinal end of the hard mask.