# US 10,872,785 B2 · QFN pin routing thru lead frame etching > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,785 B2 - Document ID: US10872785B2 - Status: Granted - Kind: B2 - Application number: 16/520,040 - Filed: 2019-07-23 - Published: 2019-11-14 - Granted: 2020-12-22 - Earliest claimed: 2016-12-23 - Assignees: Texas Instruments Incorporated - Applicants: Texas Instruments Incorporated - Inventors: Dolores Babaran Milo; Cherry Lyn Marquez Aranas - Web page: https://patentgrep.com/patent/US10872785B2 ## CPC - H10W 70/042: {Etching} - H10W 70/421: {Shapes or dispositions} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 74/114: {by a substrate and the encapsulations} - H10W 72/075: {of bond wires} - H10W 72/07553: {changes in shapes} - H10W 72/07554: {changes in dispositions} - H10W 72/537: {Multiple bond wires having different shapes} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements} - H10W 72/547: {Dispositions of multiple bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe. ## Claims ### Claim 1 A semiconductor package comprising: a die attached to a die attach pad; a first lead electrically connected to the die, the first lead including three levels; a second lead electrically connected to the die, the second lead including two levels; and a third lead electrically connected to the die, the third lead including one level, wherein each of the one, two and three levels includes a thickness, wherein each of the first lead, second lead, and the third lead includes an exposed level including a portion exposed from the semiconductor package such that, a plane along the portion of each of the first lead, second lead, and the third lead is coplanar with one surface of the semiconductor package. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the portion exposed from the semiconductor package of each of the first lead, second lead, and the third lead is coplanar. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein each level of the first lead, second lead, and the third lead is parallel to each other from a cross-sectional view of the semiconductor package. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein one of the three levels of the first lead includes a wire bond attached thereto. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein one of the two levels of the second lead includes a wire bond attached thereto. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein the one level of the third lead includes a wire bond attached thereto. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the third lead includes two portions connected by a connector. ### Claim 8 (depends on 1) The semiconductor package of claim 1 further comprising mold compound covering portions of the die, the die attach pad, the first lead, the second lead, and the third lead. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the one surface of the semiconductor package includes a surface of the mold compound. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor package is a quad flat no-leads package. ### Claim 11 A semiconductor package comprising: a die attached to a die attach pad; and a portion of a lead frame defining five planes parallel to each other, wherein a first lead includes surfaces on the five planes, a second lead includes surfaces on four of the five planes, and a third lead includes surfaces on three of the five planes, and wherein at least one of the first lead, second lead, and the third lead is electrically connected to the die, and wherein one surface of each of the first lead, the second lead, and the third lead on a common plane are exposed form the semiconductor package, and wherein the common plane is coplanar with one surface of the semiconductor package. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein at least one of the first lead, second lead, and the third lead is electrically connected to the die via wire bonds. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the first lead, the second lead, and the third lead are electrically connected to the die via a first wire bond, a second wire bond and a third wire bond respectively. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein a surface of each of the first lead, the second lead, and the third lead connected to the respective first wire bond, the second wire bond and the third wire bond are in different planes of the five planes. ### Claim 15 (depends on 11) The semiconductor package of claim 11 further comprising mold compound covering portions of the die, the die attach pad, the first lead, the second lead, and the third lead. ### Claim 16 (depends on 15) The semiconductor package of claim 15, wherein the one surface of the semiconductor package includes a surface of the mold compound. ### Claim 17 (depends on 13) The semiconductor package of claim 13, wherein the portion of the lead frame includes copper.