# US 10,872,781 B2 · Semiconductor device and a method for fabricating the same

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- Number: US 10,872,781 B2
- Document ID: US10872781B2
- Status: Granted
- Kind: B2
- Application number: 16/774,823
- Filed: 2020-01-28
- Published: 2020-07-30
- Granted: 2020-12-22
- Earliest claimed: 2016-12-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chen-Ming Lee; Fu-Kai Yang; Mei-Yun Wang
- Web page: https://patentgrep.com/patent/US10872781B2

## CPC

- H10P 50/283: {by chemical means}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer.

## Claims

### Claim 1

A semiconductor device, comprising:
an isolation insulating layer disposed over a substrate;
fin structures protruding from the isolation insulating layer, the fin structures extending in a first direction and arranged in a second direction crossing the first direction;
a first source/drain epitaxial layer and a second source/drain epitaxial layer;
a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer;
a separation isolation layer disposed between the first and second conductive contacts in the second direction;
a first dielectric layer disposed in an area formed by the separation isolation layer, the first source/drain epitaxial layer and the isolation insulating layer; and
a second dielectric layer disposed in an area formed by the separation isolation layer, the second source/drain epitaxial layer and the isolation insulating layer,
wherein the separation isolation layer is made of a different material than the first and dielectric layers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the separation isolation layer is made of one or more layers of SiN and SiCN.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the first and dielectric layers are made of SiO2.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
gate structures extending in the second direction and arranged in the first direction, each having a metal gate and a cap insulating layer disposed over the metal gate; and
a liner insulating layer disposed between the first dielectric layer and the isolation insulating layer and between the second dielectric layer and the isolation insulating layer, and made of a different material than the first dielectric layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein materials of the liner insulating layer and the separation isolation layer are different from a material of the dielectric layer.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein the liner insulating layer is made of at least one selected from the group consisting of SiN and SiCN.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein the cap insulating layer is made of at least one selected from the group consisting of SiN and SiON.

### Claim 8 (depends on 4)

The semiconductor device of claim 4, wherein the liner insulating layer is made of a same material as the separation isolation layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first and second dielectric layers are located below a level at which a distance between the first source/drain epitaxial layer and the second source/drain epitaxial layer is minimum.

### Claim 10

A semiconductor device, comprising:
an isolation insulating layer;
a first fin structure and a second fin structures, both protruding from the isolation insulating layer;
a first gate structure disposed over the first and second fin structures and having a metal gate and a cap insulating layer disposed over the metal gate;
a first source epitaxial layer disposed over a source region of the first fin structure and a first drain epitaxial layer disposed over a drain region of the first fin structure;
a second source epitaxial layer disposed over a source region of the second fin structure and a second drain epitaxial layer disposed over a drain region of the second fin structure;
a first source contact disposed on the first source epitaxial layer;
a first drain contact disposed on the first drain epitaxial layer;
a second source contact disposed on the second source epitaxial layer;
a second drain contact disposed on the second drain epitaxial layer;
a separation isolation layer continuously disposed between the first source contact and the second source contact, over the first gate structure and between the first drain contact and the second drain contact;
a first dielectric layer disposed between the separation isolation layer and the isolation insulating layer and between the first and second source epitaxial layers; and
a second dielectric layer disposed between the separation isolation layer and the isolation insulating layer and between the first and second drain epitaxial layers.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the separation isolation layer is made of one or more layers of SiN and SiCN.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the separation isolation layer includes at least two dielectric layers made of different materials from each other.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, further comprising a liner insulating layer disposed between the first dielectric layer and the isolation insulating layer and, wherein:
the first gate structure includes sidewall spacers disposed on opposing side faces of the metal gate, and
materials for the liner insulating layer, the sidewall spacers, the cap insulating layer and the separation isolation layer are different from a material of the first dielectric layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the separation isolation layer is in contact with the cap insulating layer and one of the sidewall spacers of the first gate structure.

### Claim 15

A semiconductor device, comprising:
an isolation insulating layer;
a first fin structure and a second fin structures, both protruding from the isolation insulating layer;
a first gate structure disposed over the first and second fin structures and having a metal gate, a cap insulating layer disposed over the metal gate and sidewall spacers;
a first source epitaxial layer disposed over a source region of the first fin structure and a first drain epitaxial layer disposed over a drain region of the first fin structure;
a second source epitaxial layer disposed over a source region of the second fin structure and no drain epitaxial layer disposed over a drain region of the second fin structure;
a first source contact disposed on the first source epitaxial layer;
a first drain contact disposed on the first drain epitaxial layer;
a second source contact disposed on the second source epitaxial layer;
a separation isolation layer continuously disposed between the first source contact and the second source contact, over the first gate structure and between the first drain contact and over the drain region of the second fin structure; and
a dielectric layer disposed between the separation isolation layer and the isolation insulating layer and between the first and second source epitaxial layers.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the separation isolation layer has one of an L-shape in plan view.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein:
each of the first and second fin structures comprises a pair of fin structures,
each of the first and source epitaxial layers is a merged structure having a space formed between the merged structure and the isolation insulating layer between the pair of fin structures, and
the space is filled with a same material as the dielectric layer.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein a width of the separation isolation insulating layer in contact with the sidewall spacers is smaller than a width of the separation isolation insulating layer in contact with the cap insulating layers.