# US 10,872,776 B2 · Structure and formation method of semiconductor device structure

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- Number: US 10,872,776 B2
- Document ID: US10872776B2
- Status: Granted
- Kind: B2
- Application number: 15/711,542
- Filed: 2017-09-21
- Published: 2018-01-11
- Granted: 2020-12-22
- Earliest claimed: 2015-09-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jean-Pierre Colinge; Carlos H. Diaz
- Web page: https://patentgrep.com/patent/US10872776B2

## CPC

- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10P 14/60: of insulating materials
- H10P 50/28: of insulating materials
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer. A gate dielectric layer of the gate stack adjoins the first layer and the second layer.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate;
a gate stack covering a portion of the fin structure; and
a spacer element over a sidewall of the gate stack, wherein the spacer element comprises a first layer and a second layer over the first layer, the second layer is a single dielectric layer, and a dielectric constant of the first layer is greater than a dielectric constant of the second layer, and wherein the gate stack comprises a gate dielectric layer and a metal filling layer over and surrounded by the gate dielectric layer, a sidewall of the gate dielectric layer of the gate stack is in contact with the first layer and the second layer, and a bottom surface of the second layer is higher than a bottom surface of the gate dielectric layer;
a source or drain structure over the semiconductor substrate, wherein the first layer and the second layer are between the source or drain structure and the gate stack; and
a dielectric layer over the source or drain structure, wherein the second layer is in direct contact with a top surface of the dielectric layer and a top surface of the gate stack.

### Claim 2 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the first layer is sandwiched between the second layer and the fin structure.

### Claim 3 (depends on 1)

The semiconductor device structure as claimed in claim 1, further comprising a lightly doped region in the fin structure, wherein the lightly doped region is in contact with the first layer.

### Claim 4 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the second layer extends over the gate stack.

### Claim 5 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a first contact area between the first layer and the sidewall of the gate dielectric layer is less than a second contact area between the second layer and the sidewall of the gate dielectric layer.

### Claim 6 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a bottommost surface of the first layer is substantially level with a bottommost surface of the gate dielectric layer, and a topmost surface of the first layer is lower than a topmost surface of the gate stack.

### Claim 7 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a sidewall of the second layer is aligned with a sidewall of the source or drain structure.

### Claim 8 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein the second layer covers an entirety of the source or drain structure.

### Claim 9 (depends on 1)

The semiconductor device structure as claimed in claim 1, wherein a first sidewall of the first layer in direct contact with the gate stack is substantially aligned with a second sidewall of the second layer in direct contact with the gate stack, and a third sidewall of the first layer in direct contact with the source or drain structure is substantially aligned with a fourth sidewall of the second layer in direct contact with the source or drain structure.

### Claim 10

A semiconductor device structure, comprising:
a fin structure over a semiconductor substrate;
a gate stack covering a portion of the fin structure;
a spacer element over a sidewall of the gate stack, wherein the spacer element comprises a first layer and a second layer, the second layer is a single dielectric layer, a top surface of the first layer is lower than a top surface of the second layer, a dielectric constant of the first layer is greater than a dielectric constant of the second layer, and the gate stack is in contact with the first layer and the second layer;
a source or drain structure over the semiconductor substrate, wherein the second layer extends from a sidewall of the source or drain structure to a top surface of the source or drain structure; and
a dielectric layer over the source or drain structure, wherein the second layer is in direct contact with a top surface of the dielectric layer and a top surface of the gate stack.

### Claim 11 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein the gate stack comprises a gate dielectric layer, and a dielectric constant of the gate dielectric layer is greater than the dielectric constant of the second layer.

### Claim 12 (depends on 10)

The semiconductor device structure as claimed in claim 10, wherein a first sidewall of the first layer in direct contact with the gate stack is substantially aligned with a second sidewall of the second layer in direct contact with the gate stack, and a third sidewall of the first layer in direct contact with the source or drain structure is substantially aligned with a fourth sidewall of the second layer in direct contact with the source or drain structure.

### Claim 13

A semiconductor device structure, comprising:
a gate stack covering a fin structure and including a gate dielectric layer;
a spacer element over a sidewall of the gate stack, wherein the spacer element comprises a first layer and a second layer, and wherein the second layer is separated from the fin structure by the first layer, a topmost surface of the first layer is in contact with a bottommost surface of the second layer, a dielectric constant of the first layer is greater than a dielectric constant of the second layer, and the gate dielectric layer of the gate stack is in contact with the first layer and the second layer;
a source or drain structure over the fin structure, wherein the gate stack and the source or drain structure sandwich the second layer; and
a dielectric layer over the source or drain structure, wherein the second layer is in direct contact with a top surface of the dielectric layer and a top surface of the gate stack.

### Claim 14 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the second layer extends over a top surface of the gate stack along the sidewall of the gate stack.

### Claim 15 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the dielectric layer surrounds the gate stack and the source or drain structure, and the second layer extends over an entirety of the top surface of the dielectric layer.

### Claim 16 (depends on 15)

The semiconductor device structure as claimed in claim 15, further comprising an isolation feature surrounding a lower portion of the fin structure, wherein the dielectric layer is between the second layer extending over the dielectric layer and the isolation feature.

### Claim 17 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the first layer has a first width between the gate stack and the source or drain structure, and the second layer has a second width between the gate stack and the source or drain structure, and wherein the first width is substantially equal to the second width.

### Claim 18 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the first layer is thicker than the gate dielectric layer of the gate stack and thinner than the second layer.

### Claim 19 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein the gate stack comprises a metal gate stack structure, and wherein the gate dielectric layer has a first portion sandwiched between the metal gate stack structure and the first layer and a second portion sandwiched between the metal gate stack structure and the second layer.

### Claim 20 (depends on 13)

The semiconductor device structure as claimed in claim 13, wherein a first contact area between the first layer and a first portion of the sidewall of the gate stack is less than a second contact area between the second layer and a second portion of the sidewall of the gate stack, and the first portion of the sidewall of the gate stack is aligned with the second portion of the sidewall of the gate stack.