# US 10,872,772 B2 · Semiconductor arrangement and method of manufacture

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- Number: US 10,872,772 B2
- Document ID: US10872772B2
- Status: Granted
- Kind: B2
- Application number: 16/207,809
- Filed: 2018-12-03
- Published: 2020-04-30
- Granted: 2020-12-22
- Earliest claimed: 2018-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Matthias Passlack; Martin Christopher Holland
- Web page: https://patentgrep.com/patent/US10872772B2

## CPC

- H10D 64/0116: {to Group III-V semiconductors}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs}
- H10D 62/82: Heterojunctions
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3421: {Arsenides}
- H10P 14/3442: {N-type}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor arrangement includes a semiconductor layer having a source/drain region and a first epitaxial layer over the semiconductor layer. The semiconductor arrangement includes a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer and the second epitaxial layer define a contact structure for the source/drain region.

## Claims

### Claim 1

A semiconductor arrangement, comprising:
a semiconductor layer comprising a source/drain region;
a barrier layer over the semiconductor layer;
a high-k dielectric layer over the barrier layer;
a first epitaxial layer over the semiconductor layer, wherein a sidewall of the first epitaxial layer contacts the barrier layer and the high-k dielectric layer;
a second epitaxial layer over the first epitaxial layer; and
a third epitaxial layer over the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer define a contact structure for the source/drain region.

### Claim 2 (depends on 1)

The semiconductor arrangement of claim 1, wherein:
the second epitaxial layer comprises germanium, and
a concentration of germanium in a first region of the second epitaxial layer is different than the concentration of germanium in a second region of the second epitaxial layer above the first region.

### Claim 3 (depends on 1)

The semiconductor arrangement of claim 1, wherein:
the semiconductor layer comprises a channel region, and
the high-k dielectric layer is over the channel region of the semiconductor layer.

### Claim 4 (depends on 1)

The semiconductor arrangement of claim 1, wherein the third epitaxial layer is in contact with the high-k dielectric layer.

### Claim 5 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a dielectric layer, wherein the high-k dielectric layer is separated from the third epitaxial layer by the dielectric layer.

### Claim 6 (depends on 1)

The semiconductor arrangement of claim 1, wherein the semiconductor layer comprises InGaAs.

### Claim 7 (depends on 1)

The semiconductor arrangement of claim 1, wherein the first epitaxial layer comprises phosphorus doped germanium.

### Claim 8 (depends on 7)

The semiconductor arrangement of claim 7, wherein the third epitaxial layer comprises phosphorus doped silicon.

### Claim 9 (depends on 2)

The semiconductor arrangement of claim 2, wherein the concentration of germanium in the second region is less than the concentration of germanium in the first region.

### Claim 10 (depends on 1)

The semiconductor arrangement of claim 1, wherein the third epitaxial layer comprises phosphorus doped silicon.

### Claim 11 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a dielectric layer, wherein a sidewall of the third epitaxial layer is in contact with the dielectric layer.

### Claim 12 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a metal contact layer over the third epitaxial layer, wherein the contact structure is further defined by the metal contact layer.

### Claim 13 (depends on 12)

The semiconductor arrangement of claim 12, wherein a sidewall of the third epitaxial layer is in contact with a sidewall of the metal contact layer.

### Claim 14

A semiconductor arrangement, comprising:
a semiconductor layer comprising a source/drain region;
a first epitaxial layer over the semiconductor layer;
a second epitaxial layer over the first epitaxial layer;
a dielectric layer overlying the second epitaxial layer; and
a third epitaxial layer overlying the second epitaxial layer and laterally adjacent the dielectric layer, wherein the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer define a contact structure for the source/drain region.

### Claim 15 (depends on 14)

The semiconductor arrangement of claim 14, comprising:
a high-k dielectric layer over the semiconductor layer, wherein the third epitaxial layer is spaced apart from the high-k dielectric layer by the dielectric layer.

### Claim 16 (depends on 14)

The semiconductor arrangement of claim 14, wherein the dielectric layer is in contact with a top surface of the second epitaxial layer.

### Claim 17 (depends on 14)

The semiconductor arrangement of claim 14, wherein the dielectric layer is in contact with a sidewall of the third epitaxial layer.

### Claim 18

A semiconductor arrangement, comprising:
a InGaAs layer comprising a source/drain region;
a first epitaxial layer over the InGaAs layer, wherein the first epitaxial layer comprises germanium;
a second epitaxial layer over the first epitaxial layer; and
a third epitaxial layer overlying the second first epitaxial layer, wherein:
the third epitaxial layer comprises silicon, and
the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer define a contact structure for the source/drain region.

### Claim 19 (depends on 1)

The semiconductor arrangement of claim 1, comprising a gate metallization layer over the high-k dielectric layer.

### Claim 20 (depends on 19)

The semiconductor arrangement of claim 19, wherein the gate metallization layer is in direct contact with a top surface of the high-k dielectric layer.