# US 10,872,769 B2 · Formation and in-situ etching processes for metal layers

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- Number: US 10,872,769 B2
- Document ID: US10872769B2
- Status: Granted
- Kind: B2
- Application number: 16/729,725
- Filed: 2019-12-30
- Published: 2020-04-30
- Granted: 2020-12-22
- Earliest claimed: 2018-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Po-Yu Lin; Chi-Yu Chou; Hsien-Ming Lee; Huai-Tei Yang; Chun-Chieh Wang; Yueh-Ching Pai; Chi-Jen Yang; Tsung-Ta Tang; Yi-Ting Wang
- Web page: https://patentgrep.com/patent/US10872769B2

## CPC

- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/432: {using selective deposition}
- H10P 50/266: {by vapour etching only}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

## Claims

### Claim 1

A method of fabricating a semiconductor structure, comprising:
flowing a first precursor into a deposition chamber;
purging the deposition chamber to remove at least a portion of the first precursor;
flowing a second precursor into the deposition chamber to form a sublayer of a metal layer;
purging the deposition chamber to remove at least a portion of the second precursor; and
performing a metallic halide etching (MHE) process that comprises flowing a third precursor into the deposition chamber.

### Claim 2 (depends on 1)

The method of claim 1, wherein the MHE process is performed at a temperature between about 200° C. and about 1000° C.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first or second precursor comprises at least one of titanium tetrachloride (TiCl4), pentakis-dimethylamino Tantalum (PDMAT), ammonia (NH3), and triethylaluminum (TEA).

### Claim 4 (depends on 1)

The method of claim 1, wherein the third precursor comprises a chlorine-based or a fluorine-based metal precursor.

### Claim 5 (depends on 1)

The method of claim 1, wherein the third precursor comprises at least one of tungsten fluoride (WFx), tungsten chloride (WClx), titanium chloride (TiClx), titanium fluoride (TiFx), tantalum chloride (TaClx), tin chloride (SnClx), and molybdenum chloride (MoClx), wherein x is between about 1 and about 6.

### Claim 6 (depends on 1)

The method of claim 1, wherein the MHE process is performed for a time period between about 10 s and about 300 s.

### Claim 7 (depends on 1)

The method of claim 1, wherein performing the MHE process comprises performing the MHE process without activation of a plasma.

### Claim 8 (depends on 1)

The method of claim 1, wherein the MHE process is performed at a chamber pressure between about 1 Torr and about 20 Torr.

### Claim 9 (depends on 1)

The method of claim 1, wherein a flow rate for the third precursor is between about 100 standard cubic centimeters per minute (sccm) and about 12000 sccm.

### Claim 10 (depends on 1)

The method of claim 1, wherein performing the MHE process comprises performing the MHE process without exposing the semiconductor structure to an ambient.

### Claim 11

A method of fabricating a semiconductor transistor structure, comprising:
depositing a barrier layer;
depositing a work function layer on the barrier layer;
etching, by a metallic halide etching (MHE) process, the work function layer in-situ; and
depositing a metal layer on the etched work function layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein etching the work function layer comprises performing the MHE process during an atomic layer deposition (ALD) process.

### Claim 13 (depends on 11)

The method of claim 11, wherein etching the work function layer comprises performing the MHE process after an ALD process.

### Claim 14 (depends on 11)

The method of claim 11, wherein etching the work function layer comprises flowing a precursor into a deposition chamber, wherein the precursor comprises a chlorine-based or a fluorine-based metal precursor.

### Claim 15 (depends on 11)

The method of claim 11, wherein the MHE process comprises an etching process without activation of a plasma.

### Claim 16 (depends on 11)

The method of claim 11, wherein depositing the work function layer comprises:
flowing a first precursor into a deposition chamber;
purging the deposition chamber to remove at least a portion of the first precursor;
flowing a second precursor into the deposition chamber to form a sublayer of a metal layer; and
purging the deposition chamber to remove at least a portion of the second precursor.

### Claim 17

A method, comprising:
performing a deposition cycle, comprising:
flowing a first precursor into a deposition chamber;
flowing a second precursor into the deposition chamber to form a sublayer of a metal layer; and
performing a metallic halide etching (MHE) process, comprising flowing a third precursor into the deposition chamber; and
repeating the deposition cycle to form a plurality of sublayers of the metal layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the third precursor comprises at least one of tungsten fluoride (WFx), tungsten chloride (WClx), titanium chloride (TiClx), titanium fluoride (TiFx), tantalum chloride (TaClx), tin chloride (SnClx), and molybdenum chloride (MoClx), wherein x is between about 1 and about 6.

### Claim 19 (depends on 17)

The method of claim 17, wherein the MHE process is performed without activation of a plasma.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
purging the deposition chamber to remove at least a portion of the first precursor; and
purging the deposition chamber to remove at least a portion of the second precursor.