# US 10,872,760 B2 · Cluster tool and manufacuturing method of semiconductor structure using the same

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- Number: US 10,872,760 B2
- Document ID: US10872760B2
- Status: Granted
- Kind: B2
- Application number: 15/219,512
- Filed: 2016-07-26
- Published: 2018-02-01
- Granted: 2020-12-22
- Earliest claimed: 2016-07-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Han-Wen Liao
- Web page: https://patentgrep.com/patent/US10872760B2

## CPC

- H10P 70/273: {the processing being a delineation of conductive layers, e.g. by RIE}
- H01J 37/317: for changing properties of the objects or for applying thin layers thereon, e.g. for ion implantation (H01J37/36 takes precedence)
- H01J 37/32899: {Multiple chambers, e.g. cluster tools}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 50/242: {of Group IV materials}
- H10P 50/642: {Chemical etching}
- H10P 70/20: {Cleaning during device manufacture}
- H10P 70/27: {during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers}
- H10P 72/0464: {characterised by the construction of the transfer chamber}
- H10P 72/0466: {characterised by the construction of the load-lock chamber}
- H10P 72/0471: {comprising at least one ion or electron beam chamber}
- H01J 2237/317: Processing objects on a microscale
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A cluster tool includes a polyhedral transfer chamber, at least one processing chamber, at least one load lock chamber, and an electron beam (e-beam) source. The processing chamber is connected to the polyhedral transfer chamber. The processing chamber is configured to perform a manufacturing procedure to a wafer present therein. The load lock chamber is connected to the polyhedral transfer chamber. The e-beam source is configured to performing an e-beam treatment to the wafer after the wafer is performed the manufacturing procedure.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure comprising:
depositing a first metal gate layer of a gate stack on a substrate, wherein at least one residue is formed on the first metal gate layer;
tuning a wavelength of an e-beam of an e-beam treatment from a first specific wavelength to a second specific wavelength that is different from the first specific wavelength and that is configured to remove a specific type of residue; and
performing the e-beam treatment at the second specific wavelength on the first metal gate layer to remove the residue while the first metal gate layer is exposed.

### Claim 2

A method for manufacturing a semiconductor structure comprising:
performing a first etching process to form at least one trench in a semiconductive layer, wherein the trench extends from a top of the semiconductive layer to a first depth in the semiconductive layer and not through the semiconductive layer after performing the first etching process;
tuning an energy of an e-beam of an e-beam treatment from a first specific energy level to a second specific energy level that is different from the first specific energy level and that is configured to remove a specific type of residue of the first etching process;
performing the e-beam treatment at the specific energy level on a first sidewall of the trench to remove the residue of the first etching process; and
performing a second etching process to deepen the trench in the semiconductive layer after performing the e-beam treatment, wherein the trench extends from the top of the semiconductor layer to a second depth in the semiconductor layer and not through the semiconductive layer after performing the second etching process.

### Claim 3 (depends on 2)

The method of claim 2, wherein the e-beam treatment and the first etching process are performed in the same chamber.

### Claim 4 (depends on 2)

The method of claim 2, further comprising determining energy of the e-beam according to a profile of the trench formed in the first etching process.

### Claim 5

A method for manufacturing a semiconductive structure comprising:
transferring a substrate to a processing chamber to perform a deposition procedure to form a first metal gate layer of a gate stack over the substrate, wherein the first metal gate layer is formed in an opening in a dielectric layer over the substrate and on a top surface of the dielectric layer;
tuning a property an e-beam of an e-beam treatment from a first specific property to a second specific property that is different from the first specific property and that is configured to remove a specific type of residue of the deposition procedure;
performing the e-beam treatment at the specific property on the first metal gate of the gate stack while the first metal gate layer is exposed on the top surface of the dielectric layer; and
after performing the e-beam treatment, performing a second deposition procedure to form a second metal gate layer of the gate stack over the first metal gate layer of the gate stack.

### Claim 6 (depends on 5)

The method of claim 5, wherein the performing the e-beam treatment comprises transferring the substrate from the processing chamber to an e-beam chamber.

### Claim 7 (depends on 6)

The method of claim 6, further comprising performing a measurement procedure in the e-beam chamber.

### Claim 8 (depends on 5)

The method of claim 5, wherein the e-beam treatment is an in-situ e-beam treatment.

### Claim 9 (depends on 2)

The method of claim 2, wherein performing the second etching process is such that a second sidewall of the trench is more vertical than the first sidewall.

### Claim 10 (depends on 2)

The method of claim 2, wherein performing the first etching process is such that the trench is between active regions of the semiconductive layer.

### Claim 11 (depends on 1)

The method of claim 1, further comprising, after performing the e-beam treatment, forming a second metal gate layer of the gate stack over the first metal gate layer of the gate stack.

### Claim 12 (depends on 1)

The method of claim 1, further comprising transferring the substrate to an equipment front end module (EFEM), wherein the e-beam treatment is performed in the EFEM.

### Claim 13 (depends on 12)

The method of claim 12, wherein transferring the substrate to the EFEM includes:
placing the wafer on a supporting plate in an e-beam chamber in the EFEM; and
shifting the supporting plate by a translation mechanism.

### Claim 14 (depends on 2)

The method of claim 2, wherein the first etching process is performed using a mask layer on a top surface of the semiconductive layer as an etch mask and the e-beam treatment is performed while the mask layer is on the top surface of the semiconductive layer.

### Claim 15 (depends on 5)

The method of claim 5, further comprising, after performing the e-beam treatment, removing the first metal gate layer from the top surface of the dielectric layer.

### Claim 16 (depends on 1)

The method of claim 1, wherein the first specific wavelength is configured to remove a fluorine-based type of residue and the second specific wavelength is configured to remove a metal-based type of residue.

### Claim 17 (depends on 2)

The method of claim 2, wherein the second specific energy level is configured to remove a non-fluorine-based type of residue.

### Claim 18 (depends on 5)

The method of claim 5, wherein the first specific property is configured to remove a non-fluorine-based type of residue and the second specific property is configured to remove a metal-based type of residue.

### Claim 19 (depends on 11)

The method of claim 11, further comprising performing another e-beam treatment with a third specific wavelength that is different from the second specific wavelength on the second metal gate layer.

### Claim 20 (depends on 5)

The method of claim 5, further comprising performing another e-beam treatment with a third specific property that is different from the second specific property on the second metal gate layer.