# US 10,872,677 B2 · Shift register unit, gate drive circuit and driving method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,677 B2 - Document ID: US10872677B2 - Status: Granted - Kind: B2 - Application number: 16/574,494 - Filed: 2019-09-18 - Published: 2020-07-16 - Granted: 2020-12-22 - Earliest claimed: 2019-01-10 - Assignees: Hefei Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Hefei BOE Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Yongkang Hou; Zhen Zhang - Web page: https://patentgrep.com/patent/US10872677B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure discloses a shift register unit, a gate drive circuit, and a driving method thereof, and relates to the field of display technologies. The shift register unit includes an input sub-circuit, an output control sub-circuit, and an output sub-circuit. The input sub-circuit is coupled to a first node and a first voltage terminal, and is configured to output a first voltage signal to the first node in response to an input control signal. The output control sub-circuit is coupled to the first node, a second node, and a clock signal terminal, and is configured to output an output control signal to the second node in response to the first voltage signal and a clock signal. The output sub-circuit is coupled to the second node, a DC voltage terminal, and an output terminal, and is configured to output a DC voltage signal to the output terminal under the control of the output control signal. ## Claims ### Claim 1 A shift register unit, comprising: an input sub-circuit, an output control sub-circuit, an output sub-circuit, and a noise reduction sub-circuit comprising a first noise reduction sub-circuit and a second noise reduction sub-circuit, wherein: the input sub-circuit is coupled to a first node and a first voltage terminal, and configured to output a first voltage signal supplied by the first voltage terminal to the first node in response to an input control signal; the output control sub-circuit is coupled to the first node, a second node, and a clock signal terminal, and configured to output an output control signal to the second node in response to the first voltage signal and a clock signal supplied by the clock signal terminal; the output sub-circuit is coupled to the second node, a DC voltage terminal, and an output terminal, and configured to output a DC voltage signal supplied by the DC voltage terminal to the output terminal under control of the output control signal; the first noise reduction sub-circuit is coupled to a second voltage terminal and the output control sub-circuit, and is configured to perform noise reduction on the output control sub-circuit in response to a second voltage signal supplied by the second voltage terminal; the second noise reduction sub-circuit comprises a noise reduction control sub-circuit, a second node noise reduction sub-circuit, and an output terminal noise reduction sub-circuit; the noise reduction control sub-circuit is coupled to a third voltage terminal, the first node, the second node noise reduction sub-circuit, and the output terminal noise reduction sub-circuit, and is configured to output a noise reduction control signal to the second node noise reduction sub-circuit and the output terminal noise reduction sub-circuit under control of a voltage signal at the first node and a third voltage signal supplied by the third voltage terminal; the second node noise reduction sub-circuit is coupled to the second node and is configured to perform noise reduction on the second node under control of the noise reduction control signal; and the output terminal noise reduction sub-circuit is coupled to the output terminal and is configured to perform noise reduction on the output terminal under control of the noise reduction control signal. ### Claim 2 (depends on 1) The shift register unit of claim 1, wherein: the input sub-circuit comprises a first transistor; and the first transistor has a control electrode coupled to a display input terminal to receive the input control signal, a first electrode coupled to the first voltage terminal, and a second electrode coupled to the first node. ### Claim 3 (depends on 1) The shift register unit of claim 1, wherein: the output control sub-circuit comprises a second transistor and a third transistor; the second transistor has a control electrode coupled to the first node, a first electrode coupled to the clock signal terminal, and a second electrode coupled to a control electrode of the third transistor; and the third transistor further has a first electrode coupled to the first node and a second electrode coupled to the second node. ### Claim 4 (depends on 1) The shift register unit of claim 1, wherein: the output sub-circuit comprises a fourth transistor; and the fourth transistor has a control electrode coupled to the second node to receive the output control signal, a first electrode coupled to the DC voltage terminal, and a second electrode coupled to the output terminal. ### Claim 5 (depends on 1) The shift register unit of claim 1, wherein: the first noise reduction sub-circuit comprises a fifth transistor; and the fifth transistor has a control electrode coupled to the second voltage terminal, a first electrode coupled to a common voltage terminal to receive a common voltage signal, and a second electrode coupled to the output control sub-circuit. ### Claim 6 (depends on 1) The shift register unit of claim 1, wherein: the noise reduction control sub-circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a third node; the sixth transistor has a control electrode and a first electrode coupled to the third voltage terminal, respectively, and a second electrode coupled to a control electrode of the seventh transistor; the seventh transistor further has a first electrode coupled to the third voltage terminal and a second electrode coupled to the third node; a control electrode of the eighth transistor and a control electrode of the ninth transistor are coupled to the first node respectively and the eighth transistor further has a first electrode coupled to a common voltage terminal to receive a common voltage signal and a second electrode coupled to the third node; the ninth transistor further has a first electrode coupled to the common voltage terminal to receive the common voltage signal and a second electrode coupled to the control electrode of the seventh transistor; the second node noise reduction sub-circuit comprises a tenth transistor; the tenth transistor having a control electrode coupled to the third node to receive the noise reduction control signal, a first electrode coupled to the common voltage terminal to receive the common voltage signal, and a second electrode coupled to the second node; and the output terminal noise reduction sub-circuit comprises an eleventh transistor, the eleventh transistor having a control electrode coupled to the third node to receive the noise reduction control signal, a first electrode coupled to the common voltage terminal to receive the common voltage signal, and a second electrode coupled to the output terminal. ### Claim 7 (depends on 1) The shift register unit of claim 1, wherein the shift register unit further comprises a storage sub-circuit, the storage sub-circuit being coupled to the first node and the output terminal, and being configured to store the first voltage signal received by the first node. ### Claim 8 (depends on 1) The shift register unit of claim 1, wherein: the shift register unit further comprises a reset sub-circuit; and the reset sub-circuit is coupled to a reset signal terminal, the first node, and the second node, and is configured to reset the first node and the second node in response to a reset signal provided by the reset signal terminal. ### Claim 9 (depends on 8) The shift register unit of claim 8, wherein: the reset sub-circuit comprises a twelfth transistor and a thirteenth transistor; control electrodes of the twelfth transistor and the thirteenth transistor are coupled to the reset signal terminal, respectively; the twelfth transistor further has a first electrode coupled to a common voltage terminal to receive a common voltage signal, and a second electrode coupled to the first node; and the thirteenth transistor further has a first electrode coupled to the common voltage terminal to receive the common voltage signal, and a second electrode coupled to the second node. ### Claim 10 A gate drive circuit, comprising: a plurality of cascaded shift register units, each of the cascaded shift register units comprising an input sub-circuit, an output control sub-circuit, an output sub-circuit, and a noise reduction sub-circuit comprising a first noise reduction sub-circuit and a second noise reduction sub-circuit, wherein: the input sub-circuit is coupled to a first node and a first voltage terminal, and is configured to output a first voltage signal supplied by the first voltage terminal to the first node in response to an input control signal; the output control sub-circuit is coupled to the first node, a second node, and a clock signal terminal, and is configured to output an output control signal to the second node in response to the first voltage signal and a clock signal supplied by the clock signal terminal; the output sub-circuit is coupled to the second node, a DC voltage terminal, and an output terminal, and is configured to output a DC voltage signal supplied by the DC voltage terminal to the output terminal under control of the output control signal; the first noise reduction sub-circuit is coupled to a second voltage terminal and the output control sub-circuit, and is configured to perform noise reduction on the output control sub-circuit in response to a second voltage signal supplied by the second voltage terminal; the second noise reduction sub-circuit comprises a noise reduction control sub-circuit, a second node noise reduction sub-circuit, and an output terminal noise reduction sub-circuit; the noise reduction control sub-circuit is coupled to a third voltage terminal, the first node, the second node noise reduction sub-circuit, and the output terminal noise reduction sub-circuit, and is configured to output a noise reduction control signal to the second node noise reduction sub-circuit and the output terminal noise reduction sub-circuit under control of a voltage signal at the first node and a third voltage signal supplied by the third voltage terminal; the second node noise reduction sub-circuit is coupled to the second node and is configured to perform noise reduction on the second node under control of the noise reduction control signal; and the output terminal noise reduction sub-circuit is coupled to the output terminal and is configured to perform noise reduction on the output terminal under control of the noise reduction control signal. ### Claim 11 (depends on 10) The gate drive circuit of claim 10, wherein: the input sub-circuit comprises a first transistor; and the first transistor has a control electrode coupled to a display input terminal to receive the input control signal, a first electrode coupled to the first voltage terminal, and a second electrode coupled to the first node. ### Claim 12 (depends on 10) The gate drive circuit of claim 10, wherein: the output control sub-circuit comprises a second transistor and a third transistor; the second transistor has a control electrode coupled to the first node, a first electrode coupled to the clock signal terminal, and a second electrode coupled to a control electrode of the third transistor; and the third transistor further has a first electrode coupled to the first node and a second electrode coupled to the second node. ### Claim 13 (depends on 10) The gate drive circuit of claim 10, wherein: the output sub-circuit comprises a fourth transistor; and the fourth transistor has a control electrode coupled to the second node to receive the output control signal, a first electrode coupled to the DC voltage terminal, and a second electrode coupled to the output terminal. ### Claim 14 A driving method for a gate drive circuit, comprising: providing a plurality of cascaded shift register units, each of the cascaded shift register units comprising an input sub-circuit, an output control sub-circuit, an output sub-circuit, and a noise reduction sub-circuit comprising a first noise reduction sub-circuit and a second noise reduction sub-circuit, wherein: the input sub-circuit is coupled to a first node and a first voltage terminal, and is configured to output a first voltage signal supplied by the first voltage terminal to the first node in response to an input control signal; the output control sub-circuit is coupled to the first node, a second node, and a clock signal terminal, and is configured to output an output control signal to the second node in response to the first voltage signal and a clock signal supplied by the clock signal terminal; the output sub-circuit is coupled to the second node, a DC voltage terminal, and an output terminal, and is configured to output a DC voltage signal supplied by the DC voltage terminal to the output terminal under control of the output control signal; the first noise reduction sub-circuit is coupled to a second voltage terminal and the output control sub-circuit; and the second noise reduction sub-circuit comprises a noise reduction control sub-circuit, a second node noise reduction sub-circuit, and an output terminal noise reduction sub-circuit, the noise reduction control sub-circuit being coupled to a third voltage terminal, the first node, the second node noise reduction sub-circuit, and the output terminal noise reduction sub-circuit, the second node noise reduction sub-circuit being coupled to the second node, and the output terminal noise reduction sub-circuit being coupled to the output terminal; before an input phase and at a noise reduction phase, performing, by the first noise reduction sub-circuit, noise reduction on the output control sub-circuit in response to a second voltage signal supplied by the second voltage terminal; at the input phase, outputting, by the input sub-circuit, the first voltage signal supplied by the first voltage terminal to the first node in response to the input control signal; at an output phase, outputting, by the output control sub-circuit, the output control signal to the second node in response to the first voltage signal and the clock signal supplied by the clock signal terminal; and outputting the DC voltage signal supplied by the DC voltage terminal to the output terminal under control of the output control signal, wherein the noise reduction phase further comprises: outputting, by the noise reduction control sub-circuit, a noise reduction control signal to the second node noise reduction sub-circuit and the output terminal noise reduction sub-circuit under control of a voltage signal of the first node and a third voltage signal supplied by the third voltage terminal; and performing, by the second node noise reduction sub-circuit, noise reduction on the second node and performing, by the output terminal noise reduction sub-circuit, noise reduction on the output terminal, under control of the noise reduction control signal. ### Claim 15 (depends on 14) The driving method of claim 14, wherein: each of the cascaded shift register units of the gate drive circuit comprises a reset sub-circuit which is coupled to a reset signal terminal, the first node, and the second node; and the driving method further comprises, after the output phase and at a reset phase, resetting, by the reset sub-circuit, the first node and the second node in response to a reset signal supplied by the reset signal terminal.