# US 10,872,673 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,673 B2 - Document ID: US10872673B2 - Status: Granted - Kind: B2 - Application number: 16/552,828 - Filed: 2019-08-27 - Published: 2020-06-18 - Granted: 2020-12-22 - Earliest claimed: 2018-12-14 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Toshifumi Watanabe; Naofumi Abiko; Mario Sako - Web page: https://patentgrep.com/patent/US10872673B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 7/08: Control thereof - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/30: Power supply circuits - G11C 16/32: Timing circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line. ## Claims ### Claim 1 A semiconductor memory device comprising: a memory cell; a word line connected to the memory cell; a source line connected to the memory cell; and a control circuit configured to, during a read operation on the memory cell: apply a first voltage to the word line, apply a second voltage greater than the first voltage to the word line after applying the first voltage to the word line, and apply a third voltage which is greater than the first voltage and smaller than the second voltage to the word line after applying the second voltage to the word line; apply a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and apply a fifth voltage smaller than the fourth voltage to the source line after applying the fourth voltage to the source line; apply a seventh voltage greater than the third voltage to the word line after applying the third voltage to the word line, and apply an eighth voltage which is greater than the third voltage and smaller than the seventh voltage to the word line after applying the seventh voltage to the word line; and apply a ninth voltage greater than the fifth voltage to the source line according to a timing at which the seventh voltage is applied to the word line after applying the fifth voltage to the source line, and apply the fifth voltage to the source line after applying the ninth voltage to the source line. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a sense amplifier connected to the memory cell, wherein the sense amplifier is configured to sense data stored in the memory cell while the third voltage is applied to the word line. ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to apply the fourth voltage to the source line while applying the second voltage to the word line. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein a difference in magnitude between the fourth voltage and the fifth voltage is approximately the same as a difference in magnitude between the second voltage and the third voltage. ### Claim 5 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to apply a sixth voltage greater than the fifth voltage after applying the fifth voltage to the source line. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, wherein the control circuit is configured to apply the ninth voltage to the source line while applying the seventh voltage to the word line. ### Claim 7 A semiconductor memory device comprising: a first memory cell; a second memory cell; a first source line connected to the first memory cell; a second source line connected to the second memory cell; a first transistor connected to the first source line; a second transistor connected to the second source line; and a first resistor having a first end connected to the first source line and a second end connected to the second source line, wherein during a read operation on the first and second memory cells, a first control signal is applied to a gate of the first transistor to turn on the first transistor, and a second control signal different from the first control signal is applied to a gate of the second transistor to turn off the second transistor. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, further comprising: a current supply circuit configured to selectively supply a current to the first source line and the second source line. ### Claim 9 (depends on 8) The semiconductor memory device according to claim 8, wherein the current supply circuit includes: a current source; a third transistor connected between the current source and the first source line; and a fourth transistor connected between the current source and the second source line. ### Claim 10 (depends on 7) The semiconductor memory device according to claim 7, wherein a first terminal of the first transistor is connected to the first source line, and a first terminal of the second transistor is connected to the second source line, and a second terminal of the first transistor and a second terminal of the second transistor are connected to each other. ### Claim 11 (depends on 7) The semiconductor memory device according to claim 7, further comprising: a third memory cell; a third source line connected to the third memory cell; a fifth transistor connected to the third source line; and a second resistor having a first end connected to the second source line and a second end connected to the third source line, wherein during a read operation on the first, second, and third memory cells, a third control signal different from one of the first control signal and the second control signal is applied to a gate of the fifth transistor. ### Claim 12 A method of performing a read operation on a memory cell of a semiconductor memory device comprising a word line connected to the memory cell, and a source line respectively connected to the memory cell, said method comprising: to the word line, applying a first voltage, applying a second voltage greater than the first voltage after applying the first voltage, and applying a third voltage which is greater than the first voltage and smaller than the second voltage after applying the second voltage; to the source line, applying a fourth voltage according to a timing at which the second voltage is applied to the word line, and applying a fifth voltage smaller than the fourth voltage after applying the fourth voltage; to the word line, applying a seventh voltage greater than the third voltage after applying the third voltage, and applying an eighth voltage which is greater than the third voltage and smaller than the seventh voltage after applying the seventh voltage; and to the source line, applying a ninth voltage greater than the fifth voltage according to a timing at which the seventh voltage is applied to the word line after applying the fifth voltage, and applying the fifth voltage after applying the ninth voltage. ### Claim 13 (depends on 12) The method according to claim 12, further comprising: sensing data stored in the memory cell with a sense amplifier of the semiconductor memory device while the third voltage is applied to the word line. ### Claim 14 (depends on 12) The method according to claim 12, wherein the fourth voltage is applied to the source line while applying the second voltage to the word line. ### Claim 15 (depends on 12) The method according to claim 12, wherein a difference in magnitude between the fourth voltage and the fifth voltage is approximately the same as a difference in magnitude between the second voltage and the third voltage. ### Claim 16 (depends on 12) The method according to claim 12, further comprising: to the source line, applying a sixth voltage greater than the fifth voltage after applying the fifth voltage. ### Claim 17 (depends on 12) The method according to claim 12, wherein the ninth voltage is applied to the source line while applying the seventh voltage to the word line.