# US 10,872,670 B2 · Methods for determining data states of memory cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,670 B2 - Document ID: US10872670B2 - Status: Granted - Kind: B2 - Application number: 16/221,765 - Filed: 2018-12-17 - Published: 2020-06-18 - Granted: 2020-12-22 - Earliest claimed: 2018-12-17 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Ugo Russo; Violante Moschiano; William C. Filipiak; Andrea D'Alessandro - Web page: https://patentgrep.com/patent/US10872670B2 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)} - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 2211/5621: Multilevel programming verification - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods of operating a memory, and apparatus configured to perform similar methods, include determining a voltage level of a stepped sense operation that activates a memory cell of the memory during a programming operation for the memory cell, and determining a voltage level of a ramped sense operation that activates the memory cell during a read operation for the memory cell. ## Claims ### Claim 1 A method of operating a memory, comprising: programming a first memory cell of the memory, wherein the first memory cell has a particular position relative to a respective string driver for the first memory cell; determining a voltage level of a stepped sense operation that activates the first memory cell; determining a voltage level of a ramped sense operation that activates the first memory cell; determining a difference between the voltage level of the ramped sense operation that activates the first memory cell and the voltage level of the stepped sense operation that activates the first memory cell; and determining a correction factor for a ramped sense operation of a second memory cell of the memory responsive to at least the difference between the voltage level of the ramped sense operation that activates the first memory cell and the voltage level of the stepped sense operation that activates the first memory cell. ### Claim 2 (depends on 1) The method of claim 1, wherein programming the first memory cell comprises programming a plurality of memory cells comprising the first memory cell. ### Claim 3 (depends on 2) The method of claim 2, wherein determining the voltage level of the stepped sense operation that activates the first memory cell comprises, for each memory cell of the plurality of memory cells, determining a respective voltage level of the stepped sense operation that activates that memory cell. ### Claim 4 (depends on 2) The method of claim 2, wherein determining the voltage level of the ramped sense operation that activates the first memory cell comprises, for each memory cell of the plurality of memory cells, determining a respective voltage level of the ramped sense operation that activates that memory cell. ### Claim 5 (depends on 1) The method of claim 1, wherein programming the first memory cell comprises verifying the programming of the first memory cell using a prior stepped sense operation. ### Claim 6 (depends on 5) The method of claim 5, wherein determining the voltage level of the stepped sense operation that activates the first memory cell comprises performing a stepped sense operation having a number of steps that is different than a number of steps of the prior stepped sense operation. ### Claim 7 A method of operating a memory, comprising: programming a plurality of memory cells of a memory to have respective data states of a plurality of data states, wherein each memory cell of the plurality of memory cells has a respective position relative to a respective string driver for that memory cell; for each memory cell of the plurality of memory cells: determining a respective voltage level of a stepped sense operation that activates that memory cell; determining a respective voltage level of a ramped sense operation that activates that memory cell; determining a respective difference between the respective voltage level of the ramped sense operation that activates that memory cell and the respective voltage level of the stepped sense operation that activates that memory cell; and determining a correction factor for a subsequent ramped sense operation of a memory cell of the memory, having a particular position relative to a respective string driver for that memory cell, responsive to at least the respective difference for each memory cell of the plurality of memory cells having the particular position relative to its respective string driver. ### Claim 8 (depends on 7) The method of claim 7, wherein determining the correction factor comprises determining the correction factor as a function of a voltage level of the subsequent ramped sense operation that activates its memory cell. ### Claim 9 (depends on 7) The method of claim 7, wherein programming the plurality of memory cells to have respective data states of the plurality of data states comprises, for each data state of the plurality of data states, programming a respective subset of the plurality of memory cells to have that data state. ### Claim 10 (depends on 7) The method of claim 7, further comprising determining the respective voltage level of the ramped sense operation that activates a particular memory cell prior to determining the respective voltage level of the stepped sense operation that activates the particular memory cell. ### Claim 11 (depends on 7) The method of claim 7, wherein the stepped sense operation is a subsequent stepped sense operation, the method further comprising: verifying that each memory cell of the plurality of memory cells has its respective data state using a prior stepped sense operation. ### Claim 12 (depends on 11) The method of claim 11, wherein using the prior stepped sense operation comprises using a stepped sense operation having a greater number of steps than a number of steps of the subsequent stepped sense operation. ### Claim 13 (depends on 7) The method of claim 7, wherein the method is performed during fabrication of the memory. ### Claim 14 A method of operating a memory, comprising: programming a first memory cell of the memory, wherein the first memory cell has a particular position relative to a respective string driver for the first memory cell; after programming the first memory cell, determining a voltage level of a stepped sense operation that activates the first memory cell comprising sensing a state of a data line connected to the first memory cell using a first sense circuit; after programming the first memory cell, determining a voltage level of a ramped sense operation that activates the first memory cell comprising sensing a state of the data line connected to the first memory cell using a second sense circuit different than the first sense circuit; determining a difference between the voltage level of the ramped sense operation that activates the first memory cell and the voltage level of the stepped sense operation that activates the first memory cell; and determining a correction factor for a ramped sense operation of a second memory cell of the memory responsive to at least the difference between the voltage level of the ramped sense operation that activates the first memory cell and the voltage level of the stepped sense operation that activates the first memory cell. ### Claim 15 (depends on 14) The method of claim 14, wherein determining the correction factor for the ramped sense operation of the second memory cell responsive to at least the difference between the voltage level of the ramped sense operation that activates the first memory cell and the voltage level of the stepped sense operation that activates the first memory cell further comprises determining the correction factor for the ramped sense operation of the second memory cell further responsive to the particular position of the first memory cell relative to the respective string driver for the first memory cell, and a position of the second memory cell relative to a respective string driver for the second memory cell. ### Claim 16 (depends on 14) The method of claim 14, wherein the stepped sense operation for the first memory cell comprises applying a first plurality of stepped voltage levels to a control gate of the first memory cell, wherein the ramped sense operation for the first memory cell comprises applying a second plurality of stepped voltage levels, having a greater number of steps than the first plurality of stepped voltage levels, to the control gate of the first memory cell, and wherein a length of each stepped voltage level of the second plurality of stepped voltage levels is at least one order of magnitude smaller than a length of each stepped voltage level of the first plurality of stepped voltage levels. ### Claim 17 (depends on 14) The method of claim 14, wherein the stepped sense operation for the first memory cell is a subsequent stepped sense operation, and wherein programming the first memory cell comprises performing one or more prior stepped sense operations using the first sense circuit to verify that the first memory cell has reached a desired data state of the programming. ### Claim 18 (depends on 17) The method of claim 17, wherein the one or more prior stepped sense operations for the first memory cell each comprise applying a first plurality of stepped voltage levels to a control gate of the first memory cell, wherein the subsequent stepped sense operation for the first memory cell comprises applying a second plurality of stepped voltage levels to the control gate of the first memory cell, and wherein a number of steps of the second plurality of stepped voltage levels is greater than a number of steps of the first plurality of stepped voltage levels. ### Claim 19 (depends on 14) The method of claim 14, wherein the particular position of the first memory cell relative to the string driver for the first memory cell corresponds to a first distance, and wherein a position of the second memory cell relative to a string driver for the second memory cell corresponds to a second distance, greater than the first distance, the method further comprising: programming a third memory cell of the memory, wherein the third memory cell has a position relative to a respective string driver for the third memory cell that corresponds to a third distance, greater than the second distance; after programming the third memory cell, determining a voltage level of a stepped sense operation that activates the third memory cell; after programming the third memory cell, determining a voltage level of a ramped sense operation that activates the third memory cell; and determining a difference between the voltage level of the ramped sense operation that activates the third memory cell and the voltage level of the stepped sense operation that activates the third memory cell; wherein determining the correction factor for the ramped sense operation of the second memory cell comprises: determining a first correction factor responsive to the difference between the voltage level of the ramped sense operation that activates the first memory cell and the voltage level of the stepped sense operation that activates the first memory cell; determining a second correction factor responsive to the difference between the voltage level of the ramped sense operation that activates the third memory cell and the voltage level of the stepped sense operation that activates the third memory cell; and determining the correction factor for the ramped sense operation of the second memory cell responsive to an interpolation between the first correction factor and the second correction factor. ### Claim 20 (depends on 14) The method of claim 14, further comprising determining the voltage level of the ramped sense operation that activates the first memory cell prior to determining the voltage level of the stepped sense operation that activates the first memory cell.