# US 10,872,669 B2 · Semiconductor device and a manufacturing method of the semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,669 B2 - Document ID: US10872669B2 - Status: Granted - Kind: B2 - Application number: 16/509,864 - Filed: 2019-07-12 - Published: 2020-06-25 - Granted: 2020-12-22 - Earliest claimed: 2018-12-21 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Eun Young Park - Web page: https://patentgrep.com/patent/US10872669B2 ## CPC - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A semiconductor device includes a bit line, a source line, and a memory string coupled between the bit line and the source line. The memory string includes at least one drain select transistor, a plurality of memory cells, at least one source select transistor, and a dummy transistor coupled between the bit line and the drain select transistor or between the source line and the source select transistor. ## Claims ### Claim 1 A semiconductor device comprising: a bit line; a source line; a plurality of memory strings coupled between the bit line and the source line, wherein each of the plurality of memory strings comprises: at least one drain select transistor; a plurality of memory cells; at least one source select transistor; and a dummy transistor coupled between the bit line and the drain select transistor or between the source line and the source select transistor; a peripheral circuit configured to perform an erase operation, a program operation or a read operation on the memory strings by applying bias to dummy lines coupled to dummy transistors of the memory strings; and a control logic configured to control the peripheral circuit, wherein the control logic is configured to control the peripheral circuit such that the bias varies according to threshold voltages of the dummy transistors. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the memory strings include a first memory string having a first dummy transistor with a first threshold voltage and a second memory string having a second dummy transistor with a second threshold voltage lower than the first threshold voltage, and wherein the control logic is configured to control the peripheral circuit such that bias applied to a second dummy line coupled to the second dummy transistor is lower than bias applied to a first dummy line coupled to the first dummy transistor. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the memory strings include a first memory string having a first dummy transistor with a first threshold voltage and a second memory string having a second dummy transistor with a second threshold voltage higher than the first threshold voltage, and wherein the control logic is configured to control the peripheral circuit such that bias applied to a second dummy line coupled to the second dummy transistor is higher than bias applied to a first dummy line coupled to the first dummy transistor. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein, during an erase operation: a ground voltage is applied to a dummy line coupled to the dummy transistor when a threshold voltage of the dummy transistor is equal to a reference value; a positive voltage is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is greater than the reference value; and a negative voltage is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is lower than the reference value. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein, during a program operation: a turn-on voltage, not including an offset, is applied to a dummy line coupled to the dummy transistor when a threshold voltage of the dummy transistor is equal to a reference value; a turn-on voltage, including a positive offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is greater than the reference value; and a turn-on voltage, including a negative offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is lower than the reference value. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein, during a read operation: a turn-on voltage or a turn-off voltage, not including an offset, is applied to a dummy line coupled to the dummy transistor when a threshold voltage of the dummy transistor is equal to a reference value, a turn-on voltage or a turn-off voltage, including a positive offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is greater than the reference value, and a turn-on voltage or a turn-off voltage, including a negative offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is lower than the reference value. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the read operation is a verify operation. ### Claim 8 A semiconductor device comprising: a bit line; a source line; a plurality of memory strings coupled between the bit line and the source line, wherein each of the plurality of memory strings comprises: at least one drain select transistor; a plurality of memory cells; at least one source select transistor; and a dummy transistor coupled between the bit line and the at least one drain select transistor or between the source line and the source select transistor; a peripheral circuit configured to perform an erase operation, a program operation or a read operation on the memory strings by applying bias to dummy lines coupled to dummy transistors of the memory strings; and a control logic configured to control the peripheral circuit, wherein the control logic is configured to control the peripheral circuit such that the bias varies according to junction overlaps of channel structures included in the memory strings. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the memory strings include a first memory string having a first channel structure with a first junction overlap and a second memory string having a second channel structure with a second junction overlap greater than the first junction overlap, and wherein the control logic is configured to control the peripheral circuit such that bias applied to a second dummy line coupled to a dummy transistor of the second memory string is lower than bias applied to a first dummy line coupled to a dummy transistor of the first memory string. ### Claim 10 (depends on 8) The semiconductor device of claim 8, wherein the memory strings include a first memory string having a first channel structure with a first junction overlap and a second memory string having a second channel structure with a second junction overlap smaller than the first junction overlap, and wherein the control logic is configured to control the peripheral circuit such that bias applied to a second dummy line coupled to a dummy transistor of the second memory string is higher than bias applied to a first dummy line coupled to a dummy transistor of the first memory string. ### Claim 11 (depends on 8) The semiconductor device of claim 8, wherein, during an erase operation: a ground voltage is applied to a dummy line coupled to the dummy transistor when a threshold voltage of the dummy transistor is equal to a reference value; a positive voltage is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is greater than the reference value; and a negative voltage is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is lower than the reference value. ### Claim 12 (depends on 8) The semiconductor device of claim 8, wherein, during a program operation: a turn-on voltage, not including an offset, is applied to a dummy line coupled to the dummy transistor when a threshold voltage of the dummy transistor is equal to a reference value; a turn-on voltage, including a positive offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is greater than the reference value; and a turn-on voltage, including a negative offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is lower than the reference value. ### Claim 13 (depends on 8) The semiconductor device of claim 8, wherein, during a read operation: a turn-on voltage or a turn-off voltage, not including an offset, is applied to a dummy line coupled to the dummy transistor when a threshold voltage of the dummy transistor is equal to a reference value, a turn-on voltage or a turn-off voltage, including a positive offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is greater than the reference value, and a turn-on voltage or a turn-off voltage, including a negative offset, is applied to the dummy line coupled to the dummy transistor when the threshold voltage of the dummy transistor is lower than the reference value. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the read operation is a verify operation. ### Claim 15 A semiconductor device comprising: stacked structures each including word lines, at least one select line stacked over the word lines, and at least one dummy line stacked over the at least one select line; openings passing through the stacked structures; channel layers formed in the openings; pads formed in the openings, wherein the pads are coupled to the channel layers, respectively; a peripheral circuit configured to apply bias to dummy lines during an erase operation, a program operation, or a read operation; and a control logic configured to control the peripheral circuit such that the bias varies depending on heights of the pads. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the pads include a first pad having a first height and a second pad having a second height greater than the first height, and wherein the control logic is configured to control the peripheral circuit such that bias applied to a dummy line corresponding to the second pad is lower than bias applied to a dummy line corresponding to the first pad. ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein the pads include a first pad having a first height and a second pad having a second height smaller than the first height, and wherein the control logic is configured to control the peripheral circuit such that bias applied to a dummy line corresponding to the second pad is higher than bias applied to a dummy line corresponding to the first pad. ### Claim 18 (depends on 15) The semiconductor device of claim 15, wherein the pads have a higher impurity concentration than the channel layers.