# US 10,872,662 B2 · 2T2R binary weight cell with high on/off ratio background

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- Number: US 10,872,662 B2
- Document ID: US10872662B2
- Status: Granted
- Kind: B2
- Application number: 16/448,799
- Filed: 2019-06-21
- Published: 2020-08-20
- Granted: 2020-12-22
- Earliest claimed: 2019-02-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Ryan M. Hatcher; Titash Rakshit; Jorge Kittl; Rwik Sengupta; Dharmendar Palle; Joon Goo Hong
- Web page: https://patentgrep.com/patent/US10872662B2

## CPC

- G11C 11/2259: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/221: {using ferroelectric capacitors}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- G11C 11/2273: {Reading or sensing circuits or methods}
- G11C 11/2275: {Writing or programming circuits or methods}
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 2013/0042: {Read using differential sensing, e.g. bit line [BL] and bit line bar [BLB]}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A weight cell and device are herein disclosed. The weight cell includes a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET, and a second FET and a second resistive memory element connected to a drain of the second FET. The drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET.

## Claims

### Claim 1

A weight cell, comprising:
a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET; and
a second FET and a second resistive memory element connected to a drain of the second FET,
wherein the drain of the first FET is connected to a gate of the second FET and the drain of the second FET is connected to a gate of the first FET, and wherein a source of the first FET is connected to a first output line and a source of the second FET is connected to a second output line.

### Claim 2 (depends on 1)

The weight cell of claim 1, wherein the first FET and the second FET comprise n-type FETs.

### Claim 3 (depends on 1)

The weight cell of claim 1, wherein the first FET and the second FET comprise p-type FETs.

### Claim 4 (depends on 1)

The weight cell of claim 1, wherein the first resistive memory element and the second resistive memory element comprise magneto tunnel junctions (MTJs).

### Claim 5 (depends on 1)

The weight cell of claim 1, wherein the first resistive memory element and the second resistive memory element comprise resistive random access memory (RRAM) elements.

### Claim 6 (depends on 1)

The weight cell of claim 1, wherein the first resistive memory element and the second resistive memory element comprise ferroelectric random access memory (FeRAM) elements.

### Claim 7 (depends on 1)

The weight cell of claim 1, wherein the first resistive memory element and the second resistive memory element comprise pulse code modulation (PCM) memory elements.

### Claim 8 (depends on 1)

The weight cell of claim 1, wherein the first output line comprises a first external connection and the second output line comprises a second external connection.

### Claim 9 (depends on 8)

The weight cell of claim 8, further comprising a third external connection to a lead of the first resistive memory element and a fourth external connection to a lead of the second resistive memory element.

### Claim 10 (depends on 1)

The weight cell of claim 1, further comprising a first external connection to a lead of the first resistive memory element and a second external connection to a lead of the second resistive memory element.

### Claim 11 (depends on 10)

The weight cell of claim 10, wherein the first output line comprises a third external connection and the second output line comprises a fourth external connection.

### Claim 12 (depends on 1)

The weight cell of claim 1, wherein the weight cell produces a logical value based on a conductance of the first resistive memory element and a conductance of the second resistive memory element.

### Claim 13

A device, comprising:
an array of weight cells, each weight cell including:
a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET; and
a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET being connected to a gate of the first FET; and
a processor configured to perform inference with the array of weight cells by:
setting inputs for a row of weight cells from among the array of weight cells according to a logical value of a corresponding neuron; and
reading outputs of a column of weight cells from among the array of weight cells.

### Claim 14 (depends on 13)

The device of claim 13, wherein the processor is further configured to perform inference by measuring a total current from the read outputs and dividing the total current by an output current.

### Claim 15 (depends on 13)

The device of claim 13, wherein the first resistive memory element and the second resistive memory element comprise magneto tunnel junctions (MTJs).

### Claim 16 (depends on 13)

The device of claim 13, wherein the first FETs and the second FETs comprise n-type FETs.

### Claim 17

A device, comprising:
an array of weight cells, each weight cell including:
a first field effect transistor (FET) and a first resistive memory element connected to a drain of the first FET; and
a second FET and a second resistive memory element connected to a drain of the second FET, the drain of the first FET being connected to a gate of the second FET and the drain of the second FET being connected to a gate of the first FET; and
a processor configured to write to the resistive memory elements according to a direction of a current supplied to the resistive memory elements.

### Claim 18 (depends on 17)

The device of claim 17, wherein the processor is configured to write to the resistive memory elements by fixing voltages input to the weight cell to a write voltage when the direction of the current is down.

### Claim 19 (depends on 17)

The device of claim 17, wherein the processor is configured to write to the resistive memory elements by holding currents output by the weight cell to a write voltage when the direction of the current is up.

### Claim 20 (depends on 17)

The device of claim 17, wherein the first resistive memory element and the second resistive memory element comprise magneto tunnel junctions (MTJs).