# US 10,872,661 B2 · ReRAM programming method including low-current pre-programming for program time reduction

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- Number: US 10,872,661 B2
- Document ID: US10872661B2
- Status: Granted
- Kind: B2
- Application number: 16/405,936
- Filed: 2019-05-07
- Published: 2020-10-15
- Granted: 2020-12-22
- Earliest claimed: 2019-04-10
- Assignees: Microchip Technology Incorporated
- Applicants: Microchip Technology Inc.
- Inventors: Fengliang Xue; Fethi Dhaoui; Victor Nguyen; John L. McCollum
- Web page: https://patentgrep.com/patent/US10872661B2

## CPC

- G11C 13/003: {Cell access}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0078: {Write using current through the cell}
- G11C 2013/0088: {Write with the simultaneous writing of a plurality of cells}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C 2213/74: Array wherein each memory cell has more than one access device
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

## Claims

### Claim 1

A method for programming a resistive random-access memory (ReRAM) cell including a ReRAM memory device, the method comprising:
selecting a ReRAM device to be programmed, the ReRAM device including two conductive electrodes separated by layer of a solid electrolyte material, one of the two conductive electrodes serving as an ion source;
generating a pre-programming pulse for a first period of time that passes a first current through the selected ReRAM device for the first period of time, the first current limited to a first magnitude selected to create a leakage path through the solid electrolyte layer of the selected ReRAM device, the leakage path formed from a series of one or more discontinuities in the solid electrolyte material; and
after the first period of time has terminated, generating a programming pulse that passes a second current limited to a second magnitude greater than the first magnitude through the selected ReRAM device for a second period of time shorter than the first period of time, the second magnitude selected to create a current path through the selected ReRAM device, the current path including a conductive filament that extends at least partially along the leakage path.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
determining resistance of the selected ReRAM device after passing the second current through the selected ReRAM device for the second period of time; and
repeating passing the second current through the selected ReRAM device only if the determined resistance of the selected ReRAM device is higher than a predetermined threshold value.

### Claim 3 (depends on 1)

The method of claim 1 wherein the first period of time is in the range of from about 10 μSec to about 1 mSec and the second period of time is in the range of from about 1 μSec to about 10 μSec.

### Claim 4 (depends on 3)

The method of claim 3 wherein the first period of time is about 100 μSec and the second period of time is about 1 μSec.

### Claim 5 (depends on 1)

The method of claim 1 wherein the first magnitude is between about 1 μA and about 100 μA.

### Claim 6 (depends on 1)

The method of claim 1 wherein the second magnitude is between about 100 μA and about 1 mA.

### Claim 7

A method for programming a resistive random-access memory (ReRAM) cell including a ReRAM device and at least one select transistor connected in series between a bit line and a source line, the ReRAM device including two conductive electrodes separated by layer of a solid electrolyte material, one of the two conductive electrodes serving as an ion source, the at least one select transistor having a gate connected to a word line, the method comprising:
applying a programming potential between the bit line and the source line;
applying a pre-programming voltage pulse to the word line, the pre-programming voltage pulse turning on the at least one select transistor to cause a pre-programming current limited to a first magnitude to flow through the ReRAM device, the first magnitude selected to create a leakage path through the solid electrolyte layer, the leakage path formed from a series of one or more discontinuities in the solid electrolyte material;
applying a programming voltage pulse to the word line after applying the pre-programming voltage pulse to the word line, the programming voltage pulse having a magnitude higher than the pre-programming voltage pulse, the programming voltage pulse turning on the at least one select transistor to cause a programming current limited to a second magnitude higher than the first magnitude to flow through the ReRAM device, the second magnitude selected to create a current path having a desired resistance across the ReRAM cell, the current path including a conductive filament that extends at least partially along the leakage path; and
wherein the pre-programming voltage pulse has a width larger than the programming voltage pulse.

### Claim 8 (depends on 7)

The method of claim 7 further comprising:
(a) determining the resistance of the ReRAM cell after the end of the programming voltage pulse;
(b) if the determined resistance of the ReRAM cell is higher than a predetermined threshold, applying an additional programming voltage pulse to the word line and repeating step (a);
(c) if the determined resistance of the ReRAM cell is no higher than the predetermined threshold, terminating the method.

### Claim 9 (depends on 7)

The method of claim 7 wherein the pre-programming voltage pulse has a width in the range of from about 10 μSec to about 1 mSec and the programming voltage pulse has a width in the range of from about 1 μSec to about 10 μSec.

### Claim 10 (depends on 7)

The method of claim 7 wherein the pre-programming voltage pulse has a width of about 100 μSec and the programming voltage pulse has a width of about 1 μSec.

### Claim 11 (depends on 7)

The method of claim 7 wherein the first magnitude is between about 1 μA and about 100 μA.

### Claim 12 (depends on 7)

The method of claim 7 wherein the second magnitude is between about 100 μA and about 1 mA.

### Claim 13

In an array of resistive random-access memory (ReRAM) memory cells each including a ReRAM device having two conductive electrodes separated by layer of a solid electrolyte material, one of the two conductive electrodes serving as an ion source, a method for programming comprising:
simultaneously passing a first pre-programming current through the ReRAM device in each of a selected first plurality of ReRAM memory cells for a first period of time, some of the ReRAM cells in the selected first plurality of ReRAM memory cells to be programmed in a subsequent programming step and others of the ReRAM cells in the selected first plurality of ReRAM cells not to be programmed in a subsequent programming step, the first pre-programming current limited to a first magnitude selected to create a leakage path through the solid electrolyte layer of each ReRAM device in the selected first plurality of ReRAM memory cells, the leakage path formed from a series of one or more discontinuities in the solid electrolyte material;
selecting a second plurality of ReRAM memory cells, the second plurality being a subset of the first plurality of ReRAM memory cells and including only those ones of the first plurality of cells that are to be programmed in the subsequent programming step; and
after passing the first pre-programming current through the ReRAM device in each of the selected first plurality of ReRAM memory cells, performing the subsequent programming step by simultaneously passing a programming current through the ReRAM device in each of the second plurality of ReRAM memory cells for a second period of time shorter than the first period of time, the programming current limited to a second magnitude greater than the first magnitude, the second magnitude selected to create a current path having a desired resistance across the ReRAM cell, the current path including a conductive filament that extends at least partially along the leakage path.

### Claim 14 (depends on 13)

The method of claim 13, wherein the second magnitude is selected to create a current path through the ReRAM device in each of the selected first plurality of ReRAM memory cells.

### Claim 15 (depends on 13)

The method of claim 13 wherein selecting at least one ReRAM memory cell comprises applying a programming potential between a bit line connected to the at least one ReRAM memory cell and a source line connected to the at least one ReRAM memory cell.

### Claim 16 (depends on 13)

The method of claim 13 wherein:
the simultaneous passing of the pre-programming current through the ReRAM device in each of the selected first plurality of ReRAM memory cells for the first period of time comprises turning on at least one select transistor connected in series with each ReRAM device by applying a first gate potential to the at least one select transistor, the applied first gate potential limiting the pre-programming current to the first magnitude; and
the simultaneous passing of the programming current through the ReRAM device in each of the second plurality of ReRAM memory cells for the second period of time comprises turning on the at least one select transistor by applying a second gate potential to the at least one select transistor, the second gate potential being larger than the first gate potential and limiting the programming current to the second magnitude.

### Claim 17 (depends on 13)

The method of claim 13 wherein the first period of time is in the range of from about 10 μSec to about 1 mSec and the second period of time is in the range of from about 1 μSec to about 10 μSec.

### Claim 18 (depends on 13)

The method of claim 13 wherein the first period of time is about 100 μSec and the second period of time is about 1 μSec.

### Claim 19 (depends on 13)

The method of claim 13 wherein the first magnitude is between about 1 μA and about 100 μA.

### Claim 20 (depends on 13)

The method of claim 13 wherein the second magnitude is between about 100 μA and about 1 mA.

### Claim 21

In an array containing rows and columns of ReRAM memory cells, each column of memory cells including ReRAM memory cells formed from a ReRAM device in series with at least one select transistor between a column bit line and a column source line, each row of memory cells including a word line coupled to the gate of the at least one select transistor, a programming circuit comprising:
a bit line decoder coupled to each of the bit lines in the array;
a word line decoder coupled to each of the word lines in the array;
a source line driver coupled to common source line in the array;
a memory controller coupled to the bit line decoder, the word line decoder, and the source line driver, the memory controller configured to address ReRAM cells in the array and to program selected ReRAM cells in the array by controlling the bit line decoder, the word line decoder and the source line driver to pass a pre-programming current through selected ReRAM devices in each of a selected first plurality of ReRAM memory cells for a first period of time, some of the ReRAM cells in the selected first plurality of ReRAM memory cells to be programmed in a subsequent programming step and others of the ReRAM cells in the selected first plurality of ReRAM cells not to be programmed in a subsequent programming step, the pre-programming current limited to a magnitude selected to create a leakage path through the solid electrolyte layer in each of the ReRAM devices of the selected first plurality of ReRAM memory cells, the leakage path formed from a series of one or more discontinuities in the solid electrolyte material,
the memory controller configured to select a second plurality of ReRAM memory cells, the second plurality being a subset of the first plurality of ReRAM memory cells and including only those ones of the first plurality of cells that are to be programmed in the subsequent programming step, and after passing the pre-programming current through the selected ReRAM devices performing the subsequent programming step by passing a programming current through the selected second plurality of ReRAM devices for a second period of time shorter than the first period of time, the programming current limited to a magnitude selected to create a current path through the selected-second plurality of ReRAM devices, the current path including a conductive filament that extends at least partially along the leakage path.

### Claim 22 (depends on 21)

The programming circuit of claim 21 wherein the memory controller is further configured to erase the selected ReRAM cells in the array by controlling the bit line decoder, the word line decoder and the source line driver to pass an erase current in a direction opposite the first and second currents through the selected ReRAM devices, the erase current limited to a magnitude selected to remove the current path through the selected ReRAM devices.

### Claim 23 (depends on 21)

The programming circuit of claim 21 wherein the memory controller is further configured to control the common source driver to apply ground potential to the common source line during programming and reading and to apply an erase potential to the common source line during erasing.