# US 10,872,659 B2 · Memory system having write assist circuit including memory-adapted transistors

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- Number: US 10,872,659 B2
- Document ID: US10872659B2
- Status: Granted
- Kind: B2
- Application number: 16/780,739
- Filed: 2020-02-03
- Published: 2020-06-04
- Granted: 2020-12-22
- Earliest claimed: 2017-04-18
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yangsyu Lin; Chiting Cheng; Jonathan Tsung-Yung Chang; Shang-Chi Wu
- Web page: https://patentgrep.com/patent/US10872659B2

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G03F 1/20: Masks or mask blanks for imaging by charged particle beam [CPB] radiation, e.g. by electron beam; Preparation thereof
- G03F 1/26: Phase shift masks [PSM]; PSM blanks; Preparation thereof
- G03F 1/30: Alternating PSM, e.g. Levenson-Shibuya PSM; Preparation thereof
- G03F 1/32: Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion,; Preparation thereof
- G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/18: {Peripheral circuit regions}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory system includes a first array (of memory cells) and a second array (of write assist circuits) arranged into columns each including a bit line and a bit_bar line coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array, each write assist circuit including: latch and memory-adapted third and fourth NMOS transistors. The latch includes: memory-adapted first PMOS and first NMOS transistors connected in series between a power-supply voltage and a first node selectively connectable to a ground voltage; and memory-adapted second PMOS transistor and second NMOS transistors connected in series between the power-supply voltage and a second node selectively connectable to ground voltage. The third NMOS transistor is connected in series between the first node and ground voltage; and the fourth NMOS transistor connected in series between the second node and ground voltage.

## Claims

### Claim 1

A memory system comprising:
a first array of memory cells arranged into first rows;
a second array of write assist circuits arranged into second rows;
the first array of memory cells and the second array of write assist circuits being arranged into columns;
each column including a bit line and a bit_bar line operatively coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array; and
each write assist circuit including:
a first PMOS transistor and a first NMOS transistor connected in series between a power-supply voltage and a first node, gate electrodes of the first PMOS transistor and the first NMOS transistor being connected to a second node;
a first switchable conductive path between the first node and a ground voltage;
a second PMOS transistor and a second NMOS transistor connected in series between the power-supply voltage and a third node, gate electrodes of the second PMOS transistor and the second NMOS transistor being connected to a fourth node;
a second switchable conductive path between the third node and the ground voltage;
a third NMOS transistor connected in series between the fourth node and a data line;
a first shunt connecting the fourth node and the data line;
a fourth NMOS transistor connected in series between the second node and a data_bar line; and
a second shunt connecting the second node and the data_bar line.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein the first switchable conductive path includes:
a fifth NMOS transistor connected in series between the first node and the ground voltage; and
wherein a gate electrode of the fifth NMOS transistor is configured to receive a control signal.

### Claim 3 (depends on 2)

The memory system claim 2, wherein the second switchable conductive path includes:
a sixth NMOS transistor connected in series between the third node and the ground voltage; and
wherein a gate electrode of the sixth NMOS transistor is configured to receive the control signal.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein:
the first shunt lacks a transistor; and
the second shunt lacks a transistor.

### Claim 5 (depends on 4)

The memory system of claim 4, wherein:
a gate electrode of the third NMOS transistor is connected to the first shunt; and
a gate electrode of the fourth NMOS transistor is connected to the second shunt.

### Claim 6 (depends on 1)

The memory system of claim 1, further comprising:
a fifth NMOS transistor connected in series between the first node and the ground voltage;
a sixth NMOS transistor connected in series between the third node and the ground voltage; and
wherein gate electrodes of each of the fifth NMOS transistor and the sixth NMOS transistor are connected to the ground voltage.

### Claim 7 (depends on 1)

The memory system of claim 1, wherein:
the data line is a bit line; and
the data_bar line is a bit_bar line.

### Claim 8

A memory system comprising:
a first array of memory cells arranged into first rows;
a second array of write assist circuits arranged into second rows;
the first array of memory cells and the second array of write assist circuits being arranged into columns;
each column including a bit line and a bit_bar line operatively coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array; and
each write assist circuit including:
a first PMOS transistor and a first NMOS transistor connected in series between a power-supply voltage and a first node, gate electrodes of the first PMOS transistor and the first NMOS transistor being connected to a second node, the second node being connected to a data_bar line;
a first switchable conductive path between the first node and a ground voltage;
a second PMOS transistor and a second NMOS transistor connected in series between the power-supply voltage and a third node, gate electrodes of the second PMOS transistor and the second NMOS transistor being connected to a fourth node, the fourth node being connected to a data line;
a second switchable conductive path between the third node and the ground voltage;
a third NMOS transistor having a high resistance configuration and for which a first drain/source electrode is connected to the fourth node;
a first shunt connecting the fourth node and the data line;
a fourth NMOS transistor having a high resistance configuration and for which a first drain/source electrode is connected to the second node; and
a second shunt connecting the second node and the data_bar line.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein the first switchable conductive path includes:
a fifth NMOS transistor connected in series between the first node and a fifth node;
a sixth NMOS transistor connected in series between the fifth node and the ground voltage; and
wherein a gate electrode of the fifth NMOS transistor is configured to receive a control signal.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the first switchable conductive path includes:
a gate electrode of the sixth NMOS transistor is connected to the power-supply voltage.

### Claim 11 (depends on 9)

The memory system of claim 9, wherein the second switchable conductive path includes:
a seventh NMOS transistor connected in series between the third node and a sixth node; and
an eighth NMOS transistor connected in series between the sixth node and the ground voltage; and
wherein a gate electrode of the seventh NMOS transistor is configured to receive the control signal.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the first switchable conductive path includes:
a gate electrode of the eighth NMOS transistor is connected to the power-supply voltage.

### Claim 13 (depends on 11)

The memory system of claim 11, further comprising:
a third PMOS transistor connected in series between the power-supply voltage and the gate electrode of the eighth NMOS transistor; and
wherein a gate electrode of the third PMOS transistor is configured to receive the control signal.

### Claim 14 (depends on 9)

The memory system of claim 9, further comprising:
a third PMOS transistor connected in series between the power-supply voltage and the gate electrode of the sixth NMOS transistor; and
wherein a gate electrode of the third PMOS transistor is configured to receive the control signal.

### Claim 15 (depends on 8)

The memory system of claim 8, wherein:
the first shunt lacks a transistor; and
the second shunt lacks a transistor.

### Claim 16 (depends on 8)

The memory system of claim 8, wherein:
a gate electrode of each of the third NMOS transistor and the fourth NMOS transistor is connected to the ground voltage.

### Claim 17 (depends on 8)

The memory system of claim 8, further comprising:
a fifth NMOS transistor connected in series between the first node and a fifth node;
a sixth NMOS transistor connected in series between the fifth node and the ground voltage;
a seventh NMOS transistor connected in series between the third node and a sixth node; and
an eighth NMOS transistor connected in series between the sixth node and the ground voltage; and
wherein gate electrodes of each of the fifth NMOS transistor and the eighth NMOS transistor are connected to the ground voltage.

### Claim 18 (depends on 8)

The memory system of claim 8, wherein:
a second drain/source electrode of the third NMOS transistor is connected to a fifth node;
a second drain/source electrode of the fourth NMOS transistor is connected to a sixth node; and
each write assist circuit further comprises:
a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the ground voltage; and
a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the ground voltage; and
wherein a gate electrode of each of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor is connected to the ground voltage.

### Claim 19

A memory system comprising:
a first array of memory cells arranged into first rows;
a second array of write assist circuits arranged into second rows;
the first array of memory cells and the second array of write assist circuits being arranged into columns;
each column including a bit line and a bit_bar line operatively coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array; and
each write assist circuit including:
a memory-adapted latch including:
a memory-adapted first PMOS transistor and a memory-adapted first NMOS transistor connected in series between a power-supply voltage and a first node, the first node being selectively connectable to a ground voltage; and
a memory-adapted second PMOS transistor and a memory-adapted second NMOS transistor connected in series between the power-supply voltage and a second node, the second node being selectively connectable to the ground voltage;
a memory-adapted third NMOS transistor connected in series between the first node and the ground voltage; and
a memory-adapted fourth NMOS transistor connected in series between the second node and the ground voltage;
wherein a gate electrode of each of the memory-adapted third and fourth transistors is connected to a latch-enable signal-line thereby for controlling the memory-adapted latch;
wherein the memory-adapted first and second PMOS and the memory-adapted first and second NMOS transistors are adapted for at least one of a memory power-domain, higher threshold voltages, lower saturation currents or lower leakage currents; and
whereas logic-adapted transistors are adapted for at least one of a logic power-domain, lower threshold voltages, higher saturation currents or higher leakage currents.

### Claim 20 (depends on 19)

The memory system of claim 19, wherein:
gate electrodes of the memory-adapted first PMOS transistor and the memory-adapted first NMOS transistor are connected to a third node;
gate electrodes of the memory-adapted second PMOS transistor and the memory-adapted second NMOS transistor are connected to a fourth node;
the fourth node is connected to a data line; and
the third node is connected to data_bar line.