# US 10,872,655 B2 · DRAM memory chips quick optical erasure

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- Number: US 10,872,655 B2
- Document ID: US10872655B2
- Status: Granted
- Kind: B2
- Application number: 16/235,989
- Filed: 2018-12-28
- Published: 2019-07-04
- Granted: 2020-12-22
- Earliest claimed: 2017-10-04
- Applicants: Goran Krilic
- Inventors: Goran Krilic
- Web page: https://patentgrep.com/patent/US10872655B2

## CPC

- G11C 11/409: Read-write [R-W] circuits
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52)
- G11C 11/419: Read-write [R-W] circuits
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/50: Bond wires
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/752: {between stacked chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Instant optical DRAM data erasure can be performed. In wafer level packaging (chip scale package) die is usually on top (flip-chip) and metal interconnections does not interfere with penetrating light during chip illumination. IR light penetrates through chip's thin epoxy on top and deeply into die. Light is absorbed in the die, near active layer, generating electron-hole pairs. Electron-hole pairs diffuse to chip active layer and generate discharging photocurrents in DRAM capacitors.

## Claims

### Claim 1

A Dynamic Random Access Memory chip comprising:
a substrate;
an active layer; and
data charge nodes;
wherein said Dynamic Random Memory chip is stacked between a lower chip and an upper chip, and positioned relative to a near infrared light source such that said Dynamic Random Access Memory chip is optically illuminated by said near infrared light source, near infrared light penetrates through said upper chip to be partially absorbed in said Dynamic Random Access Memory chip's substrate, generating charge carriers that diffuse to said Dynamic Random Memory chip's active layer and discharge said Dynamic Random Access Memory chip's data charge nodes.

### Claim 2 (depends on 1)

The Dynamic Random Access Memory chip of claim 1 wherein said near infrared light source comprises:
a near infrared LED;
a light guide film (LGF) containing side emitting micro near infrared LEDs;
a flat fiber (FF); and
ambient light and sunlight;
wherein said near infrared LED and light guide film and flat fiber and ambient light and sunlight emit infrared light perpendicularly to the Dynamic Random Access Memory chip surface.

### Claim 3 (depends on 1)

The Dynamic Random Access Memory chip of claim 1 wherein said Dynamic Random Memory chip is contained within a chip package and wherein said near infrared light source is attached to said chip package by integration into said chip package.

### Claim 4

A Static Random Access Memory chip comprising:
a substrate;
an active layer; and
floating data charge nodes;
wherein said Static Random Memory chip is stacked between a lower chip and an upper chip, and positioned relative to a near infrared light source such that said Static Random Access Memory chip is optically illuminated by said near infrared light source, near infrared light penetrates through said upper chip to be partially absorbed in said Static Random Access Memory chip's substrate, generating charge carriers that diffuse to said Static Random Memory chip's active layer and discharge said Static Random Access Memory chip's floating data charge nodes.

### Claim 5 (depends on 4)

The Static Random Access Memory chip of claim 4 said near infrared light source comprises:
a near infrared LED;
a light guide film (LGF) containing side emitting micro near infrared LEDs;
a flat fiber (FF); and
ambient light and sunlight;
wherein said near infrared LED and light guide film and flat fiber and ambient light and sunlight emit infrared light perpendicularly to the Static Random Access Memory chip surface.

### Claim 6 (depends on 4)

The Static Random Access Memory chip of claim 4 wherein said Static Random Memory chip is contained within a chip package and wherein said near infrared light source is attached to said chip package by integration into said chip package.