# US 10,872,654 B1 · Sub-word line driver with soft-landing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,872,654 B1 - Document ID: US10872654B1 - Status: Granted - Kind: B1 - Application number: 16/688,002 - Filed: 2019-11-19 - Granted: 2020-12-22 - Earliest claimed: 2019-11-19 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Kyuseok Lee - Web page: https://patentgrep.com/patent/US10872654B1 ## CPC - G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge} - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines - G11C 8/14: Word line organisation; Word line lay-out - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) - G11C 11/409: Read-write [R-W] circuits - G11C 13/0028: {Word-line or row circuits} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a plurality of sub-word line drivers with, each sub-word line driver configured to receive a main word line signal and configured to drive a respective local word line to at least one of an active state, a soft-landing state, an off state based on the main word line signal and a phase signal. The memory device also includes a plurality of phase drivers with each phase driver configured to generate the respective phase signal. The memory device can further include a processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers. Each sub-word line driver includes a diode-connected transistor. ## Claims ### Claim 1 An apparatus, comprising: a plurality of sub-word line drivers, each sub-word line driver configured to receive a main word line signal on a corresponding global word line and configured to drive a respective local word line to at least one of an active state, a soft-landing state, or an off state based on the respective main word line signal and a respective phase signal; a plurality of phase drivers, each phase driver of the plurality of phase drivers configured to generate the respective phase signal, each phase driver connected to a predetermined number of sub-word line drivers of the plurality of sub-word line drivers, where each sub-word line driver of the predetermined number of sub-word line drivers connect to a different global word line; and a processing device operatively coupled to each of the sub-word line drivers and each of the phase drivers, the processing device configured to drive the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines corresponding to the plurality of sub-word line drivers, wherein each sub-word line driver includes a diode-connected transistor. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein each sub-word line driver of the plurality of sub-word line drivers exclusively uses two transistors. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the two transistors include a PMOS transistor and a NMOS transistor, and the NMOS transistor is the diode-connected transistor. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the off state is at least one of a pre-charge state or an idle state. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein each of the local word lines are disposed such that no two adjacent local word lines are connected to a same phase driver. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein a voltage level of the respective local word line when in the soft-landing state is in a range of 0.2 volt to 0.4 volt. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the soft-landing voltage level is adjustable. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein each sub-word line driver of the plurality of sub-word line drivers includes a PMOS transistor to pull up the respective local word line to the active state based on a voltage of the respective phase signal and a voltage of the main word line signal, and a NMOS transistor to pull down the respective local word line to at least one of the soft-landing state or the off state based on the voltage of the respective phase signal and the voltage of the main word line signal. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein each phase driver includes a first phase circuit to set the voltage of the respective phase signal at a voltage level corresponding to the active state based on a first timing signal, a second phase circuit to set the voltage of the respective phase signal at a voltage level corresponding to the soft-landing state based on a second timing signal, and a third phase circuit to set the voltage of the respective phase signal at a voltage level corresponding to the off state based on a third timing signal, and wherein the voltage level corresponding to the soft-landing state is below the voltage level corresponding to the active state and above the voltage level corresponding to the off state. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein each phase driver is configured to generate a respective second phase signal, wherein each phase driver includes a first phase circuit to set the voltage of the respective phase signal at a voltage level corresponding to the active state based on a first timing signal, a second phase circuit to set a voltage of the respective second phase signal at a voltage level corresponding to the soft-landing state based on a second timing signal, and a third phase circuit to set the voltage of the respective second phase signal at a voltage level corresponding to the off state based on a third timing signal, and wherein the voltage level corresponding to the soft-landing state is below the voltage level corresponding to the active state and above the voltage level corresponding to the off state. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the first phase circuit sets the voltage of the phase signal at the voltage level corresponding to the active state when the first timing signal is at a first state and sets the voltage of the phase signal at a voltage level corresponding to a low voltage level when the first timing signal is at a second state. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the predetermined number of sub-word line drivers is seven. ### Claim 13 A method, comprising: driving a plurality of local word lines based on a corresponding main word line signal, the plurality of local word lines driven to at least one of an active state, a soft-landing state, or an off state using a respective local word line driver having a diode-connected transistor; generating a plurality of phase signals, each phase signal corresponding to a predetermined number of local word lines of the plurality of local word lines, each local word line of the predetermined number of local word lines corresponding to a different main word line signal; driving, based on the corresponding main word line signal and a phase signal from the plurality of phase signals, the respective local word line to the soft-landing state prior to entering the off state when transitioning from the active state to the off state so as to provide row hammer stress mitigation between adjacent local word lines of the plurality of local word lines. ### Claim 14 (depends on 13) The method of claim 13, wherein the respective local word line driver exclusively uses two transistors. ### Claim 15 (depends on 14) The method of claim 14, wherein the two transistors include a PMOS transistor and a NMOS transistor, and the NMOS transistor is the diode-connected transistor. ### Claim 16 (depends on 13) The method of claim 13, wherein the off state is one of a pre-charge state or an idle state. ### Claim 17 (depends on 13) The method of claim 13, wherein each of the local word lines are disposed such that no two adjacent local word lines receive a same phase signal. ### Claim 18 (depends on 13) The method of claim 13, wherein a voltage level of the respective local word line when in the soft-landing state is in a range of 0.2 volt to 0.4 volt. ### Claim 19 (depends on 18) The method of claim 18, wherein the soft-landing voltage level is adjustable. ### Claim 20 (depends on 13) The method of claim 13, wherein the driving of the plurality of local word lines includes pulling up the respective local word line to the active state based on a voltage of the respective phase signal and a voltage of the corresponding main word line signal, and pulling down the respective local word line to at least one of the soft-landing state or the off state based on the voltage of the respective phase signal and the voltage of the corresponding main word line signal. ### Claim 21 (depends on 20) The method of claim 20, further comprising: setting the voltage of the respective phase signal at a voltage level corresponding to the active state based on a first timing signal; setting the voltage of the respective phase signal at a voltage level corresponding to the soft-landing state based on a second timing signal; and setting the voltage of the respective phase signal at a voltage level corresponding to the off state based on a third timing signal, wherein the voltage level corresponding to the soft-landing state is below the voltage level corresponding to the active state and above the voltage level corresponding to the off state. ### Claim 22 (depends on 20) The method of claim 20, further comprising: generating a plurality of second phase signals, each second phase signal corresponding to the predetermined number of local word lines of the plurality of local word lines; setting the voltage of the respective phase signal at a voltage level corresponding to the active state based on a first timing signal; setting the voltage of the respective second phase signal at a voltage level corresponding to the soft-landing state based on a second timing signal; setting the voltage of the respective second phase signal at a voltage level corresponding to the off state based on a third timing signal, wherein the voltage level corresponding to the soft-landing state is below the voltage level corresponding to the active state and above the voltage level corresponding to the off state. ### Claim 23 (depends on 22) The method of claim 22, wherein the setting of the voltage of the respective phase signal includes: setting the voltage of the respective phase signal at the voltage level corresponding to the active state when the first timing signal is at a first state, setting the voltage of the respective phase signal at the voltage level corresponding to a low voltage level when the first timing signal is at a second state. ### Claim 24 (depends on 13) The method of claim 13, wherein the predetermined number of local word lines is seven.