# US 10,872,652 B2 · Method and apparatus for optimizing calibrations of a memory subsystem

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- Number: US 10,872,652 B2
- Document ID: US10872652B2
- Status: Granted
- Kind: B2
- Application number: 16/012,427
- Filed: 2018-06-19
- Published: 2019-12-19
- Granted: 2020-12-22
- Earliest claimed: 2018-06-19
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Rakesh L. Notani; Lakshmi Narasimha Murthy Nukala; Kai Lun Hsiung; Sukalpa Biswas; Yanzhe Liu
- Web page: https://patentgrep.com/patent/US10872652B2

## CPC

- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50008: {of impedance}
- G11C 29/50012: {of timing}
- G11C 2207/2254: Calibration
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.

## Claims

### Claim 1

An integrated circuit comprising:
a memory controller having input/output (I/O) circuitry configured to provide an interface to a dynamic random access memory (DRAM) having a plurality of banks, wherein the memory controller includes a state machine configured to:
initiate a calibration of circuitry in a physical layer of the memory controller; transmit a refresh command to the DRAM responsive to initiation of the calibration;
cause the calibration to be performed concurrent with the refresh; and
subsequent to transmitting the refresh command and concurrent with performance of a calibration on the circuitry in the physical layer and a refresh of the DRAM, cause inhibiting of a clock signal provided to and removal of power from the I/O circuitry of the memory controller for at least a remainder of the calibration;
wherein the state machine is configured to, responsive to a high priority transaction being received by the memory controller, cause the memory to abort a per-bank refresh and conduct an all-bank refresh.

### Claim 2 (depends on 1)

The integrated circuit as recited in claim 1, wherein the refresh command is a command to perform a per-bank refresh, wherein the per-bank refresh comprises successively refreshing individual ones of the plurality of banks until refreshing of the plurality of banks has been completed.

### Claim 3 (depends on 1)

The integrated circuit as recited in claim 1, wherein the refresh command is a command to perform an all-bank refresh, wherein the all-bank refresh comprises concurrently refreshing individual ones of the plurality of banks.

### Claim 4 (depends on 1)

The integrated circuit as recited in claim 1, wherein the state machine is configured to cause a calibration of a delay locked loop (DLL) in the physical layer of the memory controller.

### Claim 5 (depends on 1)

The integrated circuit as recited in claim 1, wherein the state machine is configured to cause performance of a duty cycle distortion (DCD) calibration in the physical layer of the memory controller.

### Claim 6 (depends on 1)

The integrated circuit as recited in claim 1, wherein the state machine is configured to cause an impedance calibration in the physical layer of the memory controller.

### Claim 7

A method comprising:
in a memory subsystem including a memory controller coupled to a dynamic random access memory (DRAM), initiating a calibration of circuitry in a physical layer of the memory controller;
responsive to the initiation of the calibration, transmitting a refresh command to the DRAM from input/output (I/O) circuitry of the memory controller;
responsive to receiving the refresh command, the DRAM performing a refresh concurrent with performing the calibration of the circuitry in the memory controller; and
subsequent to transmitting the refresh command, inhibiting a clock signal provided to and removing power from the I/O circuitry concurrent with performing the refresh and performing a calibration on the circuitry in the physical layer during a remainder of the calibration; wherein the state machine is configured to, responsive to a high priority transaction being received by the memory controller, cause the memory to abort a per-bank refresh and conduct an all-bank refresh.

### Claim 8 (depends on 7)

The method as recited in claim 7, wherein the refresh command is a command to perform a per-bank refresh, wherein the per-bank refresh comprises successively refreshing individual ones of a plurality of banks of the DRAM until refreshing of the plurality of banks has been completed.

### Claim 9 (depends on 7)

The method as recited in claim 7, wherein the refresh command is a command to perform an all-bank refresh, wherein the all-bank refresh comprises concurrently refreshing individual ones of a plurality of banks of the DRAM.

### Claim 10 (depends on 7)

The method as recited in claim 7, wherein performing the calibration comprises calibrating a delay locked loop (DLL) in the physical layer of the memory controller.

### Claim 11 (depends on 7)

The method as recited in claim 7, wherein performing the calibration comprises performing a duty cycle distortion (DCD) calibration in the physical layer of the memory controller.

### Claim 12 (depends on 7)

The method as recited in claim 7, wherein performing the calibration comprises performing an impedance calibration in the physical layer of the memory controller.

### Claim 13

A system comprising:
a random access memory (DRAM), the DRAM having a plurality of banks;
a memory controller having an input/output (I/O) circuitry coupled to the DRAM, the memory controller including a state machine configured to:
initiate a calibration of circuitry in a physical layer of the memory controller;
transmit a refresh command to the DRAM responsive to initiation of the calibration;
cause the calibration to be performed concurrent with the refresh; and
subsequent to transmitting the refresh command and concurrent with performance of a calibration on the circuitry in the physical layer and a refresh of the DRAM, cause inhibiting of a clock signal provided to and removal of power from the I/O circuitry for at least a remainder of the calibration; wherein the state machine is configured to, responsive to a high priority transaction being received by the memory controller, cause the memory to abort a per-bank refresh and conduct an all-bank refresh.

### Claim 14 (depends on 13)

The system as recited in claim 13, wherein the refresh command is configured to cause the memory to perform one of the following types of refreshes:
a per-bank refresh, wherein the per-bank refresh comprises successively refreshing individual ones of the plurality of banks until refreshing of the plurality of banks has been completed;
wherein the refresh command is a command to perform an all-bank refresh, wherein the all-bank refresh comprises concurrently refreshing individual ones of the plurality of banks.

### Claim 15 (depends on 13)

The system as recited in claim 13, wherein the calibration comprises one or more of the following:
calibrating a delay locked loop (DLL) in the physical layer of the memory controller;
performing a duty cycle distortion (DCD) calibration in the physical layer;
performing an impedance calibration in the physical layer.

### Claim 16 (depends on 1)

The integrated circuit of claim 1, further comprising a calibration control circuit configured to perform calibrations of circuitry implemented in the physical layer.

### Claim 17 (depends on 16)

The integrated circuit of claim 16, wherein the calibration control circuit is configured to provide calibration information to the state machine.

### Claim 18 (depends on 7)

The method of claim 7, further comprising a calibration circuit performing one or more calibrations of the circuitry in the physical layer.

### Claim 19 (depends on 13)

The system of claim 13, further comprising a calibration control circuit configured to perform one or more calibrations of the circuitry of the physical layer.