# US 10,872,651 B2 · Volatile memory device and self-refresh method by enabling a voltage boost signal

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- Number: US 10,872,651 B2
- Document ID: US10872651B2
- Status: Granted
- Kind: B2
- Application number: 16/009,222
- Filed: 2018-06-15
- Published: 2019-05-23
- Granted: 2020-12-22
- Earliest claimed: 2017-11-20
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Yuji Nakaoka
- Web page: https://patentgrep.com/patent/US10872651B2

## CPC

- G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs}
- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 2211/4067: Refresh in standby or low power modes
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A volatile memory device and a self-refresh method thereof are provided. The volatile memory device includes a dynamic memory array. The self-refresh method includes transmit a self-refresh request signal when entering a power saving mode. A voltage boost signal is periodically enabled according to the self-refresh request signal. When the enabled voltage boost signal is detected, an operating voltage for driving a self-refresh operation is pulled up to a self-refresh level. When the operating voltage is pulled up to the self-refresh level, the dynamic memory array is self-refreshed. When the self-refresh operation is completed, the operating voltage is floated.

## Claims

### Claim 1

A self-refresh method, adapted to a volatile memory device having a dynamic memory array, comprising:
when entering a power saving mode, transmitting a self-refresh request signal;
receiving a basic clock signal and a clock enabling signal by a control logic circuit;
generating an address signal by an address decoder;
storing a status information of the volatile memory device by a plurality of status registers,
wherein the status registers are directly coupled to the control logic circuit and the address decoder;
periodically enabling a voltage boost signal according to the self-refresh request signal;
when detecting, by a pull-up circuit, that the voltage boost signal is enabled, pulling an operating voltage by the pull-up circuit for driving a word line in the dynamic memory array up to a self-refresh level;
when the operating voltage is pulled up to the self-refresh level, performing a self-refresh operation on the dynamic memory array; and
when the self-refresh operation is completed, floating the operating voltage, and disabling the voltage boost signal, wherein
after pulling the operating voltage up to the self-refresh level, enabling a voltage ready signal by the pull-up circuit to notify that the operating voltage has reached the self-refresh level,
after the self-refresh operation is completed, the voltage ready signal is disabled by the pull-up circuit to wait for next self-refresh operation.

### Claim 2 (depends on 1)

The self-refresh method as claimed in claim 1, wherein after the step of pulling the operating voltage for driving the word line in the dynamic memory array to the self-refresh level, the method further comprising:
enabling a voltage ready signal to notify that the self-refresh operation can begin to be performed.

### Claim 3 (depends on 2)

The self-refresh method as claimed in claim 2, wherein the step of performing the self-refresh operation on the dynamic memory array comprises:
when detecting that the voltage ready signal is enabled, generating a refresh signal;
generating a self-refresh address according to the refresh signal; and
refreshing data corresponding to the self-refresh address in the dynamic memory array.

### Claim 4

A volatile memory device, comprising:
a dynamic memory array;
a controller, coupled to the dynamic memory array, transmitting a self-refresh request signal when entering a power saving mode, wherein the controller comprises:
a control logic circuit, receiving a basic clock signal and a clock enabling signal;
an address decoder, coupled to the control logic circuit and the dynamic memory array to generate an address signal; and
a plurality of status registers, directly coupled to the address decoder and the control logic circuit to store a status information of the volatile memory device;
a refresh signal generator, coupled to the controller, periodically enabling a voltage boost signal according to the self-refresh request signal;
a pull-up circuit, coupled to the refresh signal generator and the dynamic memory array, when the enabled voltage boost signal is detected, pulling up an operating voltage for driving a word line in the dynamic memory array to a self-refresh level; and
an input/output circuit, coupled to the dynamic memory array and the controller,
wherein, when the operating voltage is pulled up to the self-refresh level, the controller performs the self-refresh operation on the dynamic memory array,
when the self-refresh operation is completed, the pull-up circuit floats the operating voltage,
wherein when the self-refresh operation is completed, the refresh signal generator disables the voltage boost signal,
wherein after pulling the operating voltage up to the self-refresh level, the pull-up circuit enables a voltage ready signal to notify that the operating voltage has reached the self-refresh level,
wherein after the self-refresh operation is completed, the pull-up circuit disables the voltage ready signal to wait for next self-refresh operation.

### Claim 5 (depends on 4)

The volatile memory device as claimed in claim 4, wherein after the pull-up circuit pulls up the operating voltage to the self-refresh level, the pull-up circuit enables a voltage ready signal to notify the refresh signal generator that the self-refresh operation can begin to be performed.

### Claim 6 (depends on 5)

The volatile memory device as claimed in claim 5, wherein the refresh signal generator comprises:
a timer, generating a refresh signal when it is detected that the voltage ready signal is enabled; and
a refresh address generator, generating a self-refresh address according to the refresh signal and providing the self-refresh address to the controller to refresh data corresponding to the self-refresh address in the dynamic memory array.